;  #INCLUDE "APCEQU"			; NEC-APC equivalences
#NOLIST					; suppress listing
;
; Port addresses
;
; DMA controller (8237)
;
CH0_ADR	==	0X01			; CH-0 address (RW)
CH0_EXA	==	0X38			; CH-0 extended address (W)
CH0_TC	==	0X11			; CH-0 terminal count (RW)
CH1_ADR	==	0X03			; CH-1 address (RW)
CH1_EXA	==	0X3A			; CH-1 extended address (W)
CH1_TC	==	0X13			; CH-1 terminal count (RW)
CH2_ADR	==	0X05			; CH-2 address (RW)
CH2_EXA	==	0X3C			; CH-2 extended address (W)
CH2_TC	==	0X15			; CH-2 terminal count (RW)
CH3_ADR	==	0X07			; CH-3 address (RW)
CH3_EXA	==	0X3E			; CH-3 extended address (W)
CH3_TC	==	0X17			; CH-3 terminal count (RW)
DMA_ST	==	0X09			; status register (R)
DMA_CMD	==	0X09			; command register (W)
DMA_WRR	==	0X19			; write request register (W)
DMA_WSM	==	0X0B			; write single mask (W)
DMA_MODE==	0X1B			; write mode (W)
DMA_CFF	==	0X0D			; clear flip flop (W)
DMA_RTR	==	0X1D			; read temp register (R)
DMA_MC	==	0X1D			; master clear (W)
DMA_WAM	==	0X1F			; write all mask (W)
;
; Interrupt controllers (8259)
;
MIC_P0	==	0X20			; master IC port 0
MIC_P1	==	0X22			; master IC port 1
SIC_P0	==	0X28			; slave IC port 0
SIC_P1	==	0X2A			; slave IC port 1
;
; Interval timer (8253)
;
IT_CNT0	==	0X2B			; counter port 0 (RW)
IT_MOD0	==	0X2F			; counter mode port 0 (W)
IT_CNT1 ==      0X61                    ; counter port 1 (RW)
IT_MOD1 ==      0X67                    ; counter mode port 1 (W)
;
; Serial I/O controllers (8251)
;
S0_DATA	==	0X30			; data (RW)
S0_STAT	==	0X32			; status (R)
S0_CMD	==	0X32			; command (W)
S0_MSK	==	0X34			; mask (W)
S0_RS	==	0X34			; read signal (R)
S0_WS	==	0X36			; write signal (W)
S1_DATA	==	0X31			; data (RW)
S1_STAT	==	0X33			; status (R)
S1_CMD	==	0X33			; command (W)
S1_MSK	==	0X35			; mask (W)
S1_RS	==	0X35			; read signal (R)
S1_WS	==	0X37			; write signal (W)
;
; CRT controller
;
CRT_STAT==	0X40			; status (R)
CRT_PARM==	0X40			; parameter (W)
CRT_DATA==	0X42			; data (R)
CRT_CMD	==	0X42			; command (W)
CRT_IRST==	0X46			; reset interrupt (W)
;
; Graphics display controller
;
GRF_STAT==	0X41			; status (R)
GRF_PARM==	0X41			; parameter (W)
GRF_DATA==	0X43			; data (R)
GRF_CMD	==	0X43			; command (W)
;
; Keyboard controller
;
KBD_DATA==	0X48			; data (R)
KBD_BZS	==	0X48			; buzzer set (W)
KBD_STAT==	0X4A			; status (R)
KBD_BZR	==	0X4A			; buzzer reset (W)
KBD_SIG	==	0X4C			; read signal (R)
KBD_BP	==	0X4E			; read book/page (R)
KBD_SH	==	0X4E			; read shift (R)
;
; Floppy disk drive controller
;
FDD_STAT==	0X50			; read status (R)
FDD_DATA==	0X52			; data (RW)
FDD_CMD	==	0X52			; command (W)
;
; Clock and calendar device
;
CLK_DATA==	0X58			; read data (R)
CLK_SET	==	0X58			; set register (W)
;
; Arithmetic processing unit
;
APU_DATA==	0X5A			; data register (RW)
APU_STAT==	0X5E			; read status (R)
APU_CMD	==	0X5E			; write command (W)
;
; Melody processing unit
;
MEL_STAT==      0X60                    ; status register (R)
MEL_CMD ==      0X60                    ; command register (W)
;
;
; Parallel list port
;
PAR_CMD ==      0X6E                    ; command register (RW)
PAR_STAT==      0X68                    ; status register (R)
PAR_DATA==      0X6A                    ; data register (W)
PAR_CMD1==      0X6C                    ; command register (W)

#RELIST					; restore listing status