The following is a preliminary tech test for Morrow Designs:


1®   Whaô  ió thå statå oæ thå "Q¢ outpuô oæ aî RÓ latcè wheî thå 
     set input is activated? 

     [ ]   It will go to a TTL low condition
     [ ]   It will go to a TTL high condition
     [ ]   It will toggle and then return low
     [ ]   None of the above


2.   What is generally accepted as a TTL low voltage:

     [ ]  1.0 Volts and below
     [ ]  2.6 Volts and below
     [ ]  0.8 Volts and below
     [ ]  none of the above


3. What is generally considerd a TTL high voltage:

     [ ]  1.0 Volts and above
     [ ]  2.0 Volts and above
     [ ]  1.8 Volts and above
     [ ]  must be equal to VCC


4. The output of an 8 input nand gate will be high if:

     [ ]  all of the inputs are high
     [ ]  one or more of the inputs are low
     [ ]  all of the inputs are low
     [ ]  both b and c are correct
       














5.  In the circuit above the voltage on the voltmeter would read:

     [ ]   5 Volts
     [ ]  10 Volts
     [ ]   1 Volt
     [ ]   3.3 Volts
Š
6.  In the circuit above, the current meter would read:

     [ ]  1 Amp
     [ ]  .1 Amps
     [ ]  .5 Amps
     [ ]  5 Amps

7.  The voltage drop across a silicon pn junction is:
     
     [ ] .3 Volts
     [ ] .7 Volts
     [ ]  1 Volt
     [ ] .5 Volts


8. In the circuit below, the transistor:

     [ ] collector is high whenever the base is low
     [ ] collector is low regardless of the base
     [ ] will conduct if the base is a TTL low voltage
     [ ] will conduct if the base is a TTL high voltage











9® Iî  thå  circuiô  below¬  whaô  wilì  happeî  oî  thå  edgå 
   transision of the CLK input:
 
    [ ] the Q output will go high
    [ ] the Q output will go low
    [ ] the Q output will toggle
    [ ] none of the above











.pa
Š10. In the circuit below, the output of the 74125 will be:

    [ ]  A TTL low voltage
    [ ]  A 2.0 volt level
    [ ]  A TTL high voltage 










11. The 8080 and Z80 CPU chips can directly address:
    
     [ ]  64K bytes
     [ ]  64K words
     [ ]  64K bits
     [ ]  dependant upon applications


12. The Z80 and 8080 Accumulator (A register):

     [ ]  is the source and destination for I/O instructions
     [ ]  contains the result of most arithmetic instructions
     [ ]  contains the instruction currently executing
     [ ]  both a and b are correct 


13. The Z80 and 8080 Program Counter:
     
     [ ] is stored in the HL register pair
     [ ] set to 0000h whenever the CPU is reset
     [ ] set to FFFFh whenever the CPU is reset
     Û Ý pointó tï memorù address oæ instructioî currentlù executing


14.  Convert the decimal number 154 to hexadecimal:

     [ ]  C3h
     [ ]  132h
     [ ]  9Ah
     [ ]  A9h


15.  The Vertical control on a scope measures:
     
     [ ]  Voltage
     [ ]  frequency
     [ ]  time
     [ ]  current

.pa
Š16.  The Horizontal control on a scope measure:

     [ ]  Voltage
     [ ]  frequency
     [ ]  time
     [ ]  current


17. The 8080 has how many working registers (including flags):

     [ ]  7
     [ ]  32
     [ ]  8
     [ ]  16


18. A Call instruction:

     [ ] stores the current program counter on the stack
     [ ] causes a branch to a subroutine
     [ ] is normally terminated by an RET instruction
     [ ] all of the above


19®  Thå CP/Í commanä tï copù alì fileó froí disë drivå á tï disë 
     drivå b:

      [ ] Copy b:=a:*.*
      [ ] CP b:=a:*.*
      [ ] Pip a:=b:*.*
      [ ] pip b:=a:*.*


20. The CP/M BDOS entry location is:
     
      [ ] 0005h
      [ ] 0000h
      [ ] 0100h
      [ ] 0038h


21. The S-100 signal PSYNC:

     [ ] indicates the end of a bus cycle
     [ ] indicates the beginning of a bus cycle
     [ ] indicates the CPU is waiting for a clock sync pulse
     [ ] is provided to synchronize system I/O devices


22. The S-100 signal pDBIN:

     Û Ý indicateó thå CPÕ ió iî eitheò aî I/Ï oò memorù reaä cycle
     [ ] indicates the CPU is in a DMA state
     [ ] indicates dynamic memory is being refreshed
     [ ] none of the above
Š
.pa
Š23.  The Z80 CPU signal M1 (or S-100 SM1 signal):

     [ ] indicates the CPU is fetching an instruction
     [ ] indicates the CPU is executing an arithmetic operation
     [ ] indicates the CPU is recognizing an interrupt
     [ ] forces all DMA devices to release the bus


24.  DMA means:
     
     [ ] double memory address
     [ ] add memory location to the D register
     [ ] data memory access
     [ ] direct memory access


25. The term RS-232 refers to:

     [ ] a communication protocol
     [ ] typically uses +12 V and -12v levels  
     [ ] is a serial communication standard
     [ ] all of the above