TITLE 'ROM Boot for CompuPro DISK1 Controller.' ;GBCROM.a86 - 8086 ROM Boot for CompuPro Disk Controller. ; ; +-----------------------+ ; | | ; | R O M B O O T | ; | | ; +-----------------------+ ; ; COMPUPRO G & G Engineering ; Oakland, CA San Leandro, Ca ; ; Copyright 1981, G and G Engineering ; ; This product is a copyright program product ; of CompuPro and is supplied for use with the ; CompuPro IEEE 696 Floppy Disk Controller. ; ; Version number: 2.2G ; Version date: 81 December 14 ROMFWA EQU *O * 100H ; Assembly Constants FDPORT EQU 0C0H ;Base port address for Controller FDCS EQU FDPORT ;Status register FDCD EQU FDPORT+1 ;Data register DMA EQU FDPORT+2 ;Dma address (when write) INTS EQU FDPORT+2 ;Status Register (when read) ; Input on port disables boot rom. SER EQU FDPORT+3 ;Serial port DELCNT EQU 5*1000 ;5 MHz processor ; Controller function definitions ; Specify (00) command NSEC EQU 0 ;Sect verify number F.RTK EQU 02 ;Read track F.SPEC EQU 03 ;Specify F.DSTS EQU 04 ;Drive status F.RDAT EQU 06 ;Read data F.RECA EQU 07 ;recalibrate F.RSTS EQU 08 ;Read status F.SEEK EQU 0FH ;Seek SRT EQU 16-8 ;= Shuggart 800s ; 16-3 ;= Shuggart 850s ; 16-3 ;= Remex HUT: EQU 240/16 ;Head unload = 240 ms HLT: EQU (35+1)/2 ;Head load = 35 ms ND: EQU 00 ;Set DMA mode ORG ROMFWA LOC 0 nop nop nop nop db 0dbh,0fdh ;8085 IN 0FDH for Dual processor swap START: xor ax,ax mov ds,ax ROM1: LD CX,#20 ;Wait 20 MSec LD BX,#ROM2 ;Return from delay JMP DELAY ROM2: LD bx,#DATA ; Output beginning DMA address LD CH,#LDMA ADDR: LD AL,[BX] OUTB DMA ;set DMA INC bx DEC CH JNZ ADDR ;if NOT all 3 bytes ; Load Specify Command LD CH,#LSPEC SPEC1: INB FDCS OR AL,AL JNS SPEC1 ;if no master ready bit LD AL,[BX] ;load command byte OUTB FDCD ;to controller INC bx DEC CH JNZ SPEC1 ;if more bytes ; Recalibrate drive LD CH,#LRECAL RCAL1: INB FDCS OR AL,AL JNS RCAL1 ;if no master ready bit ld AL,[BX] ;load command byte OUTB FDCD ;to controller INC bx DEC CH JNZ RCAL1 ;if more bytes RCAL2: INB INTS OR AL,AL JNS RCAL2 ;If not complete LD AL,#F.RSTS OUTB FDCD LD CX,#250 ;Leave light on .25 seconds LD BX,#RCAL3 ;set return address JMP DELAY RCAL3: INB FDCS OR AL,AL JNS RCAL3 INB FDCD SUB AL,#20H MOV CL,AL RCAL4: INB FDCS OR AL,AL JNS RCAL4 INB FDCD OR AL,CL jnz error ;If error in recalibrate ; Now set-up read command ld bx,#read LD CH,#LREAD READ1: INB FDCS OR AL,AL JNS READ1 ;if no master ready bit LD AL,[BX] ;load command byte OUTB FDCD ;to controller INC bx DEC CH JNZ READ1 ;if more bytes READ2: INB INTS OR AL,AL JNS READ2 ;If not complete READ3: INB FDCS OR AL,AL JNS READ3 INB FDCD SUB AL,#40H MOV BL,AL READ4: INB FDCS OR AL,AL JNS READ4 INB FDCD SUB AL,#80H MOV BH,AL LD CH,#7-2 READ5: INB FDCS OR AL,AL JNS READ5 ;if not ready INB FDCD ;read status DEC CH JNZ READ5 ;wait until all done MOV AL,BL OR AL,BH jz GOBOOT ;If no error during read SPACE 4,10 ; Error during read or recalibrate. ERROR: LD CX,#1000 ;Wait 1 second before retry LD BX,#ROM2 ; JMP DELAY SPACE 4,10 ; Delay a period of time. ; ; ENTRY CX = number of milliseconds to delay. ; BX = return address. DELAY: LD AL,#DELCNT/26 DLAY1: INC CX DEC CX DEC AL JNZ DLAY1 DEC CX MOV AL,CH OR AL,CL JNZ DELAY JMP BX ;return to caller SPACE 4,10 ; Function data for controller to boot DATA DB 0 ;Extended DB HIGH BOOT DB LOW BOOT LDMA EQU *-DATA SPEC DB F.SPEC VFD 4\SRT,4\HUT VFD 7\HLT,1\ND LSPEC EQU *-SPEC RECAL DB F.RECA,0 LRECAL EQU *-RECAL READ: DB F.RDAT DB 0 ;hds,ds1,ds0 DB 0 ;C = sector ID info DB 0 ;Head DB 1 ;Record (first sector) DB 0 ;N DB 4 ;EOT (last sectors) DB 7 ;GPL DB 128 ;DTL LREAD EQU *-READ ; Next instruction is executed when the 8086 ; resets. It appears as if the instruction is at ; 0ffff0h. ; ORG romfwa+100h-10h ds (100h-10h) - * jmp start,0 ; Next instruction disables rom, shadow ; of next instruction must be jump to ; execute boot code just loaded at 100h ; ORG ROMFWA+100h-4 ;Leave exact room DS (100H-4) - * GOBOOT: LD CL,#HIGH ROMFWA ;pass board switch value to Boot INB SER ;must preceed Boot immediately BOOT: END