'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1 subttl '(c) 1981 Morrow Designs' title 'MPZ-80 MON4.45-M FIRMWARE' .z80 0000' aseg ;**************************************************************** ;* * ;* Decision one CPU firmware, for the Morrow Designs / Thinker * ;* Toys Decision one computer. The monitor routine looks for * ;* the power on jump addresses on CPU switches which determine * ;* address to begin execution (top 5 switches). I/O is through * ;* the Wunderbus I/O motherboard UART 1. Base address of the * ;* I/O is assumed to be standard (beginning at port 48H). * ;* If top five switches are 'On', a hard disk is assumed to be * ;* the disk device and Boothd is executed. * ;* * ;* Revised 8/27/82 - M16 home and load constants * ;* changed. group0-3 equates now * ;* set int en bit high. * ;* * ;* Bobby Dale Gifford and Bob Groppo * ;* 10/20/81 * ;* * ;**************************************************************** org 0 ;Local Ram in task zero 0200 tempstk equ 0200h ;temporary stack 0000 nop equ 0 01B0 gobuff equ 01b0h ;location of task switch routine on 'RESET' 00C3 jmpop equ 0c3h ;Jump unstruction op-code 00CD callop equ 0cdh ;z80 call instruction opcode 002B t1mask equ 2bh ;unlimited mask... no traps enabled 002B t0mask equ 2bh ;unlimited mask 0036 ssmode equ 036h ;single step mode mask 001A hstrap equ 1Ah ;allow traps on halts and stops, interrupts ;- masked out in task 0 (temporary) 0001 window equ 01h ;task 0 window at location 10000 000D ACR equ 0Dh ;carriage return 000A ALF equ 0Ah ;line feed 0020 ASP equ ' ' ;space 000C AFF equ 0Ch ;form feed 0007 BEl equ 07H ;bell 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-1 '(c) 1981 Morrow Designs' 0008 BSP equ 08H ;backspace 0019 mskofst equ 19h ;offset to get to user's mask reg. contents 0017 spofst equ 17h ;offset to stack pointer of user 0015 afofst equ 15h ;offset to user Af register 0013 hlofst equ 13h ;offset to user h,l register 0011 deofst equ 11h ;offset to d,e 000F bcofst equ 0Fh ;offset to b,c 000D pcofst equ 0Dh ;offset to the users pc register 0076 nxtbyte equ 076h ;byte after a halt 0016 ersav equ regsav + 2 ;temporary error save area ;**************************************************************** ;* * ;* Wunderbus I/O equates: * ;* * ;**************************************************************** 0048 base equ 048h ;I/O base address of wunderbus ports 0008 group0 equ 08h 0009 group1 equ 09h ;serial port 1 000A group2 equ 0ah ;serial port 2 000B group3 equ 0bh ;serial port 3 004F grpctl equ base+7 ;I/O group select port ; UART equates 0048 dll equ base ;divisor latch lsb 0049 dlm equ base+1 ;divisor latch msb 0049 ier equ base+1 ;interupt enable register 004B lcr equ base+3 ;line control register 004C mcr equ base+4 ;modem control register 004D lsr equ base+5 ;line status register 0048 rbr equ base ;read data buffer 0048 thr equ base ;transmitter data buffer 0080 dlab equ 80h ;divisor latch access bit 0020 thre equ 20h ;status line TBE 0001 dr equ 01 ;line status DR bit 0001 wls0 equ 01 ;word length select bit 0 0002 wls1 equ 02 ;word length select bit 1 (for 8 bit word) 0004 stb equ 04 ;stop bit count (2 stop bits) 0000 imask equ 00 ;non interupt mode 0010 loop equ 010h ;UART loop mode ; PIC equates 0010 init equ 010h ;bit high to initialize the PIC 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-2 '(c) 1981 Morrow Designs' 004C icw1 equ base + 4 ;PIC initialization control word 1 004D icw2 equ base + 5 ;PIC initialization control word 2 004D icw3 equ base + 5 ;PIC initialization control word 3 004D icw4 equ base + 5 ;PIC initialization control word 4 004D ocw1 equ base + 5 ;PIC interrupt mask register 004C ocw2 equ base + 4 ;PIC EOI register 00FF picmask equ 0ffh ;mask to turn all interrupts off 0008 ltim equ 08h ;level triggered mode 0004 adi4 equ 04h ;call address intervals = 4 0000 adi8 equ 00h ;call address intervals = 8 0002 sngl equ 02 ;sole system PIC 0001 ic4 equ 01h ;icw4 access bit 0000 lovect equ 0 ;call vectors begin at 0 0000 hivect equ 0 ;call vectors begin at 0 0000 normal equ 0 ;Master/Reg. nest/unbuffered/no AEOI/8085 ; -normal setting of OCW4 for Morrow Software 0020 eoi equ 20h ;non-specific EOI constant ;**************************************************************** ;* * ;* HDC Winchester controller equates * ;* * ;**************************************************************** 000D revnum equ 13 0050 ioaddr equ 120Q 0050 contrl equ ioaddr 0050 status equ ioaddr 0053 data equ ioaddr+3 0052 functn equ ioaddr+2 0051 commd equ ioaddr+1 0051 secstat equ ioaddr+1 0001 dread equ 1 0001 sector equ 1 0002 opdone equ 2 0004 complt equ 4 0008 header equ 10Q 0005 drenbl equ 5 0007 dskrun equ 7 0020 ready equ 40Q 0080 system equ 200Q 00F8 stepo equ 370Q 00FC drivea equ 374Q 0001 trk0 equ 1 ;**************************************************************** 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-3 '(c) 1981 Morrow Designs' ;* * ;* DJ-DMA Equates * ;* * ;**************************************************************** 104A djstat equ 104ah ;adjusted channel address of status byte ;**************************************************************** ;* * ;* DMA Winchester Controller Equates * ;* * ;**************************************************************** 0099 cyl equ 153 ;number cylinders for Seagate ST-506 0004 heads equ 4 ;number heads for Seagate ST-506 001E stpdly equ 01eh ;15 msec for Seagate ST-506 00C8 hdsetl equ 0C8h ;20 msec for Seagate ST-506 0003 secsiz equ 3 ;512 byte sectors for Micronix 0000 readat equ 0 ;DMA controller read sector opcode 0001 write equ 1 ;DMA controller write sector opcode 0002 rhead equ 2 ;DMA controller read header opcode 0003 format equ 3 ;DMA controller format track opcode 0004 const equ 4 ;load drive constants command 0005 sense equ 5 ;return drive status command 0006 noop equ 6 ;command used when seeking 0054 dmarst equ 54h ;DMA controller reset port 0055 attn equ 55h ;DMA controller Attention port 0010 stepout equ 10h ;Step direction to track 0 0000 stepin equ 0 ;Step direction away from track 0 0001 track0 equ 1 ;track 0 status 0002 wfault equ 2 ;write fault condition from drive 0004 dready equ 4 ;drive ready status 0008 sekcmp equ 8 ;seek complete status 0011 hdspt equ 17 ;number of sectors per track 1050 iopb equ 1050h ;pointer to the channel 1080 chan equ 1080h ;actual channel 1083 select equ chan + 3 ;select byte in channel 1084 dmaddr equ chan + 4 ;24 bit dma address location 1087 arg equ chan + 7 ;beginning of four arguments to commands 108B cmmd equ chan + 11 ;actual command location 108C statis equ chan + 12 ;controller return status location 108D link equ chan + 13 ;link field address for next command 1100 bootad equ 1100h ;dma address for first sector from hddma 00FF good equ 0ffh ;good status result 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-4 '(c) 1981 Morrow Designs' ;**************************************************************** ;* * ;* Decision One Ram variables, visible only to task 0. * ;* * ;**************************************************************** 0000 ram equ $ ;Local RAM, visible only to task 0 ;**************************************************************** ;* * ;* Supervisor entry point, this jump must be inserted into the * ;* CPU's ram by the supervisor for subsequent entry to the * ;* supervisor when traps occur. * ;* * ;**************************************************************** 0000 C3 0000 super: jp super ;Supervisor entry point 0003 C3 0003 user: jp user ;(7) User entry point 0006 00 ctask: db 0 ;Current task 0007 00 cmask: db 0 ;Current mask contents 0008 0000 cstack: dw 0 ;temporary save stack 000A 0000 u.sp: dw 0 000C 0000 u.pc: dw 0 000E 0000 u.de: dw 0 0010 0000 u.hl: dw 0 0012 0000 u.af: dw 0 0014 begsav equ $ 0014 0000 regsav: dw 0 ;address of beginning of reg save area 0016 ds 1Ch 0032 monstk equ $ ;monitor stack area 0032 ds (200h - 01eh) - monstk ;******************************************************** ;* * ;* Initialized stack at 200h contents * ;* * ;******************************************************** 01E2 0000 retstk: dw 0 ;return address from call to monitor or super 01E4 0000 tskmsk: dw 0 01E6 0000 t.pc: dw 0 01E8 0000 t.sp: dw 0 ;users stack pointer 01EA 0000 t.af: dw 0 ;primary A & f register save 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-5 '(c) 1981 Morrow Designs' 01EC 0000 t.bc: dw 0 ;primary b & c register save 01EE 0000 t.de: dw 0 ;primary d & e register save 01F0 0000 t.hl: dw 0 ;primary h & l register save 01F2 0000 t.int: dw 0 ;interrupt register register save 01F4 0000 t.ix: dw 0 ; ix register save 01F6 0000 t.iy: dw 0 ; iy register save 01F8 0000 t.af1: dw 0 ; alternate A & f register save 01FA 0000 t.bc1: dw 0 ; alternate b & c register save 01FC 0000 t.de1: dw 0 ; alternate d & e register save 01FE 0000 t.hl1: dw 0 ; alternate h & l register save ;**************************************************************** ;* * ;* The following map is used to hold an image of the current * ;* memory map for all tasks. * ;* * ;**************************************************************** 0200 map: ds 200h ;Task Memory map image ;**************************************************************** ;* * ;* Decision One local I/O map, the following registers are * ;* memory mapped into task 0, and are always visible to task * ;* zero only. * ;* * ;**************************************************************** 0400 locio equ $ ;Local I/O, visible only to task 0 0400 trpadd: ds 0 ;Trapp address register (read) 0400 dspseg: ds 1 ;Display segment register (write) 0401 keybd: ds 0 ;Key board register (read) 0401 dspcol: ds 1 ;Display column register (write) 0402 switch: ds 0 ;CPU switch port (read) 0402 task: ds 1 ;Task register (write) 0403 stats: ds 0 ;Trap status register (read) 0403 mask: ds 1 ;Task mask register (write) 0404 elocio equ $ ;End of local I/O 0404 ds 200h-(elocio-locio) ;Fill out local I/O ;**************************************************************** ;* * 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-6 '(c) 1981 Morrow Designs' ;* The following ram is the actual memory map, it can only be * ;* written into, so an image is kept in the local ram. * ;* * ;**************************************************************** 0600 mapram: ds 200h ;Memory Map RAM, visible only to task 0 ;**************************************************************** ;* * ;* Decision One prom routines, usable by the supervisor task * ;* but not accessible by any other tasks. * ;* * ;**************************************************************** 0800 rom0 equ $ ;Local ROM, visible only to task 0 ;and is visible only during RESET ;**************************************************************** ;* * ;* Reset is executed only once. Currently, reset forms an * ;* identity map for task zero to occupy the first 64K of main * ;* memory, allows task 0 to have unlimited priviledges. Task1 * ;* occupies the first 64K, unlimited access and the traps are * ;* set for halts or a stop. All other task maps are initialized * ;* starting at bank 2 to bank 15. (e.g. task 15 has bank 15). * ;* If swithches are set with S1 through S7 off and S8 on, the * ;* power on jump address will be F800. If switch 6 is on, the * ;* program will jump to the monitor regardless of the state * ;* of the other switches. If S1 - S5 are all 'ON' a MORROW * ;* hard disk is assumed and the 'Boothd' program is executed. * ;* If pin 2 of 15D is lifted, the diag nostic mode is entered. * ;* * ;**************************************************************** ; Check all the readable registers 0800 D3 FF regrd: out (0ffh),a ;sync 0802 21 0400 ld hl,trpadd 0805 7E ld a,(hl) ;read trap address reg @ 400h 0806 23 inc hl 0807 7E ld a,(hl) ;read keyboard reg @ 401h 0808 23 inc hl 0809 7E ld a,(hl) ;read switch reg @ 402h 080A 23 inc hl 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-7 '(c) 1981 Morrow Designs' 080B 7E ld a,(hl) ;read trap status reg @ 403h 080C 18 4C jr getsw ; Check all the writable registers 080E AF regwr: xor a ;loop till switch not 00 080F D3 FF regwr1: out (0ffh),a ;sync 0811 32 0403 ld (mask),a ;write to the mask register 0814 32 0401 ld (dspcol),a ;write to the display column register 0817 32 0401 ld (keybd),a ;write to the display segment reg. 081A 2F cpl 081B FE FF cp 0ffh 081D 28 F0 jr z,regwr1 081F 18 39 jr getsw ; Check the Map RAMs 0821 AF tmap: xor a ;write to map ram / protection ram 0822 21 0600 ld hl,mapram 0825 D3 FF out (0ffh),a ;sync 0827 77 ld (hl),a ;write location 600,0 0828 23 inc hl 0829 77 ld (hl),a ;write 601,0 082A 2F cpl 082B 77 ld (hl),a ;write 601,0ffh 082C 2B dec hl 082D 77 ld (hl),a ;write 600,0ffh 082E 21 07FE ld hl,mapram + 01feh 0831 77 ld (hl),a ;write 7fe,0ff 0832 23 inc hl 0833 77 ld (hl),a ;write 7ff,0ff 0834 2F cpl 0835 77 ld (hl),a ;write 7ff,00 0836 2B dec hl 0837 77 ld (hl),a ;write 7fe,00 0838 18 20 jr getsw ; Check the R/W RAMs 083A 21 0000 tram: ld hl,0000h ;write to read/write ram 083D D3 FF out (0ffh),a 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-8 '(c) 1981 Morrow Designs' 083F AF tram1: xor a 0840 77 ld (hl),a ;write a 00 to ram 0841 BE cp (hl) ;read it back 0842 2F cpl 0843 77 ld (hl),a ;write an ffh to ram 0844 BE cp (hl) ;read it back 0845 CB 44 bit 0,h 0847 20 11 jr nz,getsw 0849 21 03FF ld hl,03ffh 084C 18 F1 jr tram1 ;write to 3ffh a ffh ; Check the Floating Point Processor 084E AF tfpp: xor a ;check FPP 084F D3 FF out (0ffh),a ;sync 0851 32 0C00 ld (0c00h),a ;write a 00 to location C00h 0854 32 0C08 ld (0c08h),a ;write a 00 to location C08h 0857 3A 0C00 ld a,(0c00h) ;read c00h 085A 3A 0401 getsw: ld a,(keybd) 085D CB 4F bit 1,a 085F CA 08D8 reset: jp z,reset0 ;go to the montior if low 0862 3A 0402 ld a,(switch) 0865 CB 57 bit 2,a 0867 CA 08D8 jp z,reset0 ;go to the monitor if S6 is on 086A E6 70 and 070h ;strip insignificant bits 086C CB 0F rrc a ;4 byte offset 086E CB 0F rrc a 0870 21 0BD0 ld hl,jtable ;point to beginning of table 0873 85 add a,l 0874 6F ld l,a 0875 E9 jp (hl) ; Check the S-100 bus addr and data lines 0876 21 0402 tbus: ld hl,task 0879 3E F0 ld a,0f0h 087B 77 ld (hl),a ;force upper task bits high 087C 3E FF ld a,0ffh ;init the T0 map 087E 32 061E ld (61eh),a 0881 3E 03 ld a,03 0883 32 061F ld (61fh),a 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-9 '(c) 1981 Morrow Designs' 0886 32 0603 ld (603h),a 0889 AF xor a 088A 32 0602 ld (602h),a 088D D3 FF out (0ffh),a ;sync 088F 32 FFFF ld (0ffffh),a ;write - bus addresses A0-23 are high 0892 77 ld (hl),a ;upper task bits low 0893 32 1000 ld (1000h),a ;write - bus addresses A0-23 are low 0896 F6 F0 or 0f0h 0898 77 ld (hl),a ;force upper task bits high 0899 3A FFFF ld a,(0ffffh) ;read - bus addresses A0-23 are high 089C AF xor a 089D 77 ld (hl),a ;force upper task bits low 089E 3A 1000 ld a,(1000h) ;read - bus addresses A0-23 are low 08A1 18 B7 jr getsw 08A3 21 0402 ntbus: ld hl,task 08A6 3E A0 ld a,0A0h 08A8 77 ld (hl),a ;force upper task bits high 08A9 3E AA ld a,0aah ;init the T0 map 08AB 32 061E ld (61eh),a 08AE 3E 03 ld a,03 08B0 32 061F ld (61fh),a 08B3 32 0603 ld (603h),a 08B6 3E 55 ld a,55h 08B8 32 0602 ld (602h),a 08BB D3 FF out (0ffh),a ;sync 08BD 2F cpl 08BE 32 FAAA ld (0faaah),a ;write - bus addresses A0-23 = AAAAAA 08C1 3E 50 ld a,50h 08C3 77 ld (hl),a ;upper task bits low = 5 08C4 F6 05 or 05h 08C6 32 1555 ld (1555h),a ;write - bus addresses A0-23 are low 08C9 3E A0 ld a,0A0h 08CB 77 ld (hl),a ;force upper task bits high 08CC 3A FAAA ld a,(0faaah) ;read - bus addresses A0-23 are high 08CF 3E 50 ld a,050h 08D1 77 ld (hl),a ;force upper task bits low 08D2 3A 1555 ld a,(1555h) ;read - bus addresses A0-23 are low 08D5 C3 085A jp getsw ; Initialize the maps and jump vectors 08D8 CD 08E4 reset0: call reset1 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-10 '(c) 1981 Morrow Designs' 08DB CD 0B2B call uartst 08DE CD 091D call setup 08E1 C3 01B0 jp gobuff 08E4 21 0000 reset1: ld hl,super ;initialize 'super' to the monitor... 08E7 2B settle: dec hl ;wait for hardware to settle down 08E8 7D ld a,l 08E9 B4 or h 08EA 20 FB jr nz,settle 08EC 36 C3 ld (hl),jmpop ;- this will be overwritten by the 08EE 23 inc hl ;- supervisor but all traps in the 08EF 36 00 ld (hl),00h ;- meantime will fall into the monitor. 08F1 23 inc hl 08F2 36 10 ld (hl),10h 08F4 21 0200 ld hl,map 08F7 22 0008 ld (cstack),hl ;initialize a temporary stack 08FA AF reslop: xor a 08FB 0E 03 ld c,3 ;New access priviledges 08FD 47 reslp2: ld b,a ;New allocation = segment # 08FE CD 0B18 call rstmap ;Allocate it 0901 3C inc a ;Next segment # 0902 E6 0F and 0fh ;Check if all done 0904 20 F7 jr nz,reslp2 ;Continue until done 0906 3E 10 LD A,10h ;write new task and segment 0908 06 00 LD B,0 ;TASK 1 gets first 64K of memory 090A CD 0B18 reslp1: call rstmap ;Give TASK 1 a full 64k of space 090D 04 inc B 090E 3C inc A 090F FE 20 cp 20h 0911 20 F7 jr nz,reslp1 0913 47 fmap: ld b,a ;fill all the tasks' maps 0914 CD 0B18 call rstmap 0917 3C inc a 0918 FE 00 cp 0h 091A 20 F7 jr nz,fmap 091C C9 ret 091D AF setup: xor a 091E 32 0602 ld (mapram + 2),a ;a window for DMA device commands 0921 32 0202 ld (map + 2),a ;image map updated 0924 32 0016 ld (ersav),a ;null the error save byte 0927 3E 1A ld a,hstrap ;initialize the mask register 0929 32 0403 ld (mask),a ; -to trap on halts and stops 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-11 '(c) 1981 Morrow Designs' 092C 32 0007 ld (cmask),a ; Following code checks for presence of any ram in system 092F 21 FFFF ld hl,0ffffh ;top of ram 0932 3E F0 ramchk: ld a,0f0h 0934 A4 and h 0935 28 12 jr z,badram ;dont go below task0,seg1 0937 77 ld (hl),a ;check it with a 00h 0938 BE cp (hl) 0939 28 03 jr z,nexchk 093B 2B dec hl ;try the next location 093C 18 F4 jr ramchk 093E 2F nexchk: cpl 093F 77 ld (hl),a ;check it with an ff (might be ROM) 0940 BE cp (hl) 0941 22 0017 ld (ersav + 1),hl ;store it away for printing 0944 28 11 jr z,tstsw 0946 2B dec hl ;try next location 0947 18 E9 jr ramchk 0949 21 0BAD badram: ld hl,0badh 094C 22 0017 ld (ersav + 1),hl 094F 3E 4D ld a,'M' 0951 32 0016 ld (ersav),a 0954 C3 0A6B jp allerr ;if no ram force entry to monitor 0957 3A 0402 tstsw: ld a,(switch) ;get contents of switch 095A E6 F8 and 0f8h ;Ignore irrelevent bits 095C 57 ld d,a ;d & e contain jump address 095D 1E 00 ld e,0H 095F FE 00 cp 0 ;boot hard disk if switches are all on 0961 CA 0AA3 jp z,boothd 0964 FE 08 cp 08h ;If switch 5 is off others are on 0966 CA 09F7 jp z,nuboot ; - boot DMA controller 0969 FE 10 cp 10h ;If switches 4 is off, others on 096B 28 5C jr z,djdma ; - boot the DJ-DMA floppy device 096D 3A 0402 check: ld a,(switch) ;test monitor switch 0970 CB 57 bit 2,a 0972 3E 01 ld a,1 ;normal task number 0974 ED 53 000C ld (u.pc),de ;initialize the pc save area 0978 32 0006 ld (ctask),a 097B 28 05 jr z,montor ;jump if monitor desired 097D 32 0602 ld (mapram + 2),a 0980 18 04 jr nutask 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-12 '(c) 1981 Morrow Designs' 0982 AF montor: xor a ;monitor task number 0983 11 0915 ld de,cold ;monitor location 0986 21 01B0 nutask: ld hl,gobuff ;Write a routine to switch to new task 0989 36 3E ld (hl),03eh ;- because when the task register is 098B 23 inc hl ;- written into, the lower half of the 098C 77 ld (hl),a ;- prom goes away. 098D 23 inc hl 098E 36 32 ld (hl),032h 0990 23 inc hl 0991 36 02 ld (hl),02h 0993 23 inc hl 0994 36 04 ld (hl),04h 0996 23 inc hl 0997 36 00 ld (hl),nop ;6 nops for countdown sequence 0999 23 inc hl 099A 36 00 ld (hl),nop 099C 23 inc hl 099D 36 00 ld (hl),nop 099F 23 inc hl 09A0 36 00 ld (hl),nop 09A2 23 inc hl 09A3 36 00 ld (hl),nop 09A5 23 inc hl 09A6 36 00 ld (hl),nop 09A8 23 inc hl 09A9 36 C3 ld (hl),0c3h ;the jump op code 09AB 23 inc hl 09AC 73 ld (hl),e 09AD 23 inc hl 09AE 72 ld (hl),d ;**************************************************************** ;* * ;* Wunderbuss I/O and Mult I/O PIC initialization rou- * ;* tine. Interrupt vectors = restart locations. * ;* * ;**************************************************************** 09AF AF picset: xor a 09B0 D3 4F out (grpctl),a 09B2 3E 67 ld a,lovect + hivect + init + ltim + adi8 + sngl + icw4 09B4 D3 4C out (icw1),a ;initialize the first word 09B6 3E 00 ld a,hivect 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-13 '(c) 1981 Morrow Designs' 09B8 D3 4D out (icw2),a ;initialize the second word 09BA 3E 00 ld a,normal 09BC D3 4D out (icw4),a ;initialize the forth word 09BE 3E FF ld a,picmask 09C0 D3 4D out (ocw1),a ;mask all interrupts 09C2 3E 20 ld a,eoi ;send PIC an End of Interrupt word 09C4 D3 4C out (ocw2),a ;clear the master interrupt requests 09C6 D3 4C out (ocw2),a ;clear the slaves interrupt requests 09C8 C9 ret ;**************************************************************** ;* * ;* DJ-DMA floppy disk boot routine (5.25 or 8 inch). * ;* * ;**************************************************************** 09C9 26 10 djdma: ld h,10h ; wait byte for 1 minute 09CB 01 0000 djlop0: ld bc,0000h 09CE 3A 104A djloop: ld a,(djstat) ;read the status back 09D1 FE 40 cp 040h 09D3 ED 5B 1048 ld de,(djstat - 2) ;d & e point to cold boot loader 09D7 28 94 jr z,check ;if good status continue set gobuff 09D9 FE FF cp 0ffh ; - else loop for good status 09DB 28 14 jr z,nstat ;if 0ffh then force to a zero 09DD 0B dec bc 09DE 78 ld a,b 09DF B1 or c 09E0 20 EC jr nz,djloop 09E2 25 dec h 09E3 20 E6 jr nz,djlop0 ;continue looping till a minute elapses ; DJ-DMA not responding correctly 09E5 0E 46 ld c,'F' 09E7 3A 104A ld a,(djstat) 09EA 47 ld b,a ;save the error status 09EB 3A 1048 ld a,(djstat - 2) 09EE 57 ld d,a 09EF 18 71 jr derror ;go to error--controller not ; - responding 09F1 AF nstat: xor a 09F2 32 104A ld (djstat),a ;null status byte ... signal DJ-DMA 09F5 18 D7 jr djloop 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-14 '(c) 1981 Morrow Designs' ;**************************************************************** ;* * ;* Hard Disk Boot program for the DMA Winchester Controller. * ;* * ;**************************************************************** 09F7 01 0010 nuboot: ld bc,endboot - bootbl ;byte count 09FA 21 0BB3 ld hl,bootbl ;source 09FD 11 1080 ld de,chan ;destination 0A00 ED B0 ldir ;move the command 0A02 21 1050 ld hl,iopb ;point to default channel addr 0A05 36 80 ld (hl),80h ;fill in the command channel address 0A07 AF xor a 0A08 23 inc hl ; -located at 50h to point to channel 0A09 77 ld (hl),a ; -at 80h. 0A0A 23 inc hl 0A0B 77 ld (hl),a 0A0C D3 54 out (dmarst),a ;send the controller a reset 0A0E 11 0010 ld de,010h 0A11 15 hdrl: dec d ;wait for controller to process reset 0A12 20 FD jr nz,hdrl 0A14 CD 0A3E call cloop 0A17 21 FFFF home: ld hl,-1 ;seek to home 0A1A 22 1081 ld (chan + 1),hl ;- with ffff step pulses 0A1D 3E 06 ld a,noop 0A1F 32 108B ld (statis - 1),a ;null the command byte 0A22 3E 01 ld a,1 0A24 32 108C ld (statis),a ;initialize the status byte 0A27 CD 0A3E call cloop 0A2A 11 1080 rdata: ld de,chan ;destination 0A2D 01 000D ld bc,endrd - rdtbl ;byte count 0A30 21 0BC3 ld hl,rdtbl ;source 0A33 ED B0 ldir ;move the read sector command 0A35 CD 0A3E call cloop 0A38 11 0100 ld de,0100h ;point to beginning of DMA boot prog. 0A3B C3 096D jp check 0A3E 0E 20 cloop: ld c,020h 0A40 D3 55 cloop0: out (attn),a 0A42 11 0000 ld de,0000h 0A45 3A 108C cloop1: ld a,(statis) ;check drive status 0A48 FE FF cp 0ffh ;an FF means command completed 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-15 '(c) 1981 Morrow Designs' 0A4A C8 ret z 0A4B 1B dec de ;wait for controller to respond 0A4C 7B ld a,e 0A4D B2 or d 0A4E 20 F5 jr nz,cloop1 ;give it a couple seconds to respond ; Fall through to here on any error 0A50 3A 108C ld a,(statis) 0A53 FE 01 cp 01h 0A55 20 03 jr nz,cloop2 0A57 0D dec c ;give it 10 tries if not rdy error 0A58 20 E6 jr nz,cloop0 ; - about 20 seconds 0A5A D1 cloop2: pop de ;re-align the stack pointer 0A5B 0E 48 ld c,'H' ;save the device 0A5D 47 ld b,a ;save the status 0A5E 3A 108B ld a,(cmmd) ;save the command 0A61 57 ld d,a ;**************************************************************** ;* * ;* Enter here if DISK controllers don't respond correctly. * ;* Routine alters gobuff to point to the monitor cout routine. * ;* * ;**************************************************************** 0A62 derror: 0A62 79 ld a,c 0A63 21 0016 ld hl,ersav 0A66 77 ld (hl),a ;store c for later 0A67 23 inc hl 0A68 70 ld (hl),b ;error status 0A69 23 inc hl 0A6A 72 ld (hl),d ;command causing error 0A6B AF allerr: xor a 0A6C 32 0006 ld (ctask),a 0A6F 11 0915 ld de,cold ;pointer to error print 0A72 ED 53 000C ld (u.pc),de ;save the pointer in t1 pc 0A76 C3 0986 jp nutask ;**************************************************************** ;* * 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-16 '(c) 1981 Morrow Designs' ;* Hard Disk Boot program for Decision 1 EPROM. * ;* For M26, M10, and M20. * ;* 11/4/81 BJG * ;**************************************************************** 0A79 11 0000 hdclop: ld de,0000h 0A7C DB 50 hdlop1: in a,(status) 0A7E A0 and b 0A7F C0 ret nz 0A80 1B dec de 0A81 7A ld a,d 0A82 B3 or e 0A83 20 F7 jr nz,hdlop1 0A85 18 12 jr hdcerr 0A87 26 10 wait: ld h,010h 0A89 11 0000 wait0: ld de,0 0A8C DB 50 wait1: in a,(status) 0A8E A0 and b 0A8F C8 ret z 0A90 1B dec de 0A91 7A ld a,d 0A92 B3 or e 0A93 20 F7 jr nz,wait1 0A95 25 dec h 0A96 20 F1 jr nz,wait0 0A98 E1 pop hl ;re-align the stack pointer 0A99 0E 44 hdcerr: ld c,'D' ; D for HDCA error flag 0A9B DB 50 in a,(status) ;get the primary status 0A9D 47 ld b,a 0A9E DB 51 in a,(secstat) ;get the secondary status 0AA0 57 ld d,a 0AA1 18 BF jr derror 0AA3 3E FC boothd: ld a,drivea ;select 0AA5 D3 52 out (functn),a ; drive A 0AA7 3E 05 ld a,drenbl ;turn on drive 0AA9 D3 50 out (contrl),a ; command register 0AAB 06 20 rloop: ld b,ready 0AAD CD 0A87 call wait 0AB0 3E 07 ld a,dskrun ;enable the 0AB2 D3 50 out (contrl),a ; controller 0AB4 DB 50 waitz: in a,(status) ;test for heads at track 0 0AB6 1F rra 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-17 '(c) 1981 Morrow Designs' 0AB7 30 0F jr nc,sdone 0AB9 3E F8 ld a,stepo ;execute 0ABB D3 52 out (functn),a ; the 0ABD 3E FC ld a,drivea ; step out 0ABF D3 52 out (functn),a ; command 0AC1 06 04 waitc: ld b,complt 0AC3 CD 0A79 call hdclop 0AC6 18 EC jr waitz 0AC8 DB 50 sdone: in a,(status) ;get an image 0ACA 4F ld c,a ; of the status reg 0ACB DB 50 iwait1: in a,(status) ;wait for 0ACD 91 sub c ; the index pulse 0ACE 28 FB jr z,iwait1 ; to arrive 0AD0 DB 50 iwait2: in a,(status) ;wait for the 0AD2 91 sub c ; next index pulse 0AD3 20 FB jr nz,iwait2 ;test for head settle 0AD5 DB 50 iwait3: in a,(status) 0AD7 91 sub c 0AD8 28 FB jr z,iwait3 0ADA 3E 08 ld a,header ;reset the 0ADC D3 51 out (commd),a ; buffer pointer 0ADE AF xor a ; to header area 0ADF D3 53 out (data),a ;head 0 0AE1 D3 53 out (data),a ;track 0 0AE3 3C inc a ;sector 1 0AE4 D3 53 out (data),a 0AE6 3E 80 ld a,system ;system key 0AE8 D3 53 out (data),a 0AEA 3E 01 ld a,dread ;issue a 0AEC D3 51 out (commd),a ; read command 0AEE 06 02 waitd: ld b,opdone 0AF0 CD 0A79 call hdclop 0AF3 DB 53 in a,(data) ;low order byte of 0AF5 6F ld l,a ; bootstrap address 0AF6 5F ld e,a 0AF7 DB 53 in a,(data) ;high order byte of 0AF9 67 ld h,a ; bootstrap address 0AFA 57 ld d,a 0AFB E6 F0 and 0f0h ;check for 1st segment of task0 0AFD 28 11 jr z,dxloop 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-18 '(c) 1981 Morrow Designs' 0AFF AF xor a 0B00 32 0602 ld (mapram + 2),a ;T0 map is as normal with no window 0B03 DB 53 lloop: in a,(data) ;load 0B05 12 ld (de),a ; the 0B06 1C inc e ; bootstrap 0B07 20 FA jr nz,lloop 0B09 54 ld d,h ;save the boot addr for later 0B0A 5D ld e,l 0B0B 3E 01 ld a,01 0B0D C3 096D jp check 0B10 7A dxloop: ld a,d 0B11 E6 0F and 0fh ;strip the segment # 0B13 F6 10 or 010h ; force the load into seg 0 task 1 0B15 57 ld d,a 0B16 18 EB jr lloop ;**************************************************************** ;* * ;* Rstmap writes the tasks memory allocation vectors. Upon * ;* entry the registers must contain: * ;* a = task number / task segment number to update * ;* high nibble = task # low nibble = segment # * ;* b = New allocation vector * ;* c = New allocation access * ;* * ;* Routine calculates the expression 600+(Accumulator) x 2 * ;* where accumulator contents are as listed above. All arit- * ;* hmetic and numbers are in Hex * ;* * ;**************************************************************** 0B18 6F rstmap: ld l,a ;Get task and segment numbers 0B19 26 00 ld h,0h 0B1B 29 add hl,hl ;multiply times 2 0B1C EB ex de,hl ;save calculated offset in D,E 0B1D 21 0600 ld hl,mapram ;point to beginning of ram map 0B20 CD 0B26 call rstmxx 0B23 21 0200 ld hl,map ;point to image map at 200 0B26 19 rstmxx: add hl,de ;add offset to selected map 0B27 70 ld (hl),b ;write the allocation vector to ram 0B28 23 inc hl ;point to access ram 0B29 71 ld (hl),c ;write access attributes to ram 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-19 '(c) 1981 Morrow Designs' 0B2A C9 ret ;******************************************************** ;* * ;* The following code intitializes the I/O for * ;* the Decision 1 Motherboard and the Mult I/O. * ;* * ;******************************************************** 0B2B 16 03 uartst: ld d,3 ;start with uart 3 0B2D 7A uarts0: ld a,d 0B2E D3 4F out (grpctl),a 0B30 AF xor a 0B31 D3 4D out (lsr),a ;clear line status register 0B33 D3 49 out (ier),a ;initialialize interupt mask (off) 0B35 15 dec d 0B36 20 F5 jr nz,uarts0 0B38 D3 4F out (grpctl),a ;select sense switch port 0B3A DB 49 in a,(base+1) 0B3C 07 rlca 0B3D 07 rlca 0B3E 07 rlca 0B3F E6 07 and 07h ;mask insignificant bits 0B41 FE 07 cp 07h ;all off? 0B43 16 00 ld d,0 0B45 28 0B jr z,default ;default if all off 0B47 21 0BA5 ld hl,btable ;point to baud rate table 0B4A 87 add a,a 0B4B 5F ld e,a 0B4C 19 add hl,de ;offset to selected baud rate 0B4D 4E ld c,(hl) 0B4E 23 inc hl 0B4F 46 ld b,(hl) ;bc = baud rate divisor value (D) 0B50 18 03 jr setit 0B52 default: 0B52 01 000C ld bc,12 ;default baud rate is 9600 0B55 14 setit: inc d 0B56 7A ld a,d 0B57 D3 4F out (grpctl),a 0B59 3E 87 ld a,dlab+wls1+wls0+stb 0B5B D3 4B out (lcr),a ;divisor access bit is on 0B5D 78 ld a,b 0B5E D3 49 out (dlm),a ;load high divisor register 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-20 '(c) 1981 Morrow Designs' 0B60 79 ld a,c 0B61 D3 48 out (dll),a ;load low divisor register 0B63 3E 07 ld a,wls1+wls0+stb 0B65 D3 4B out (lcr),a ;divisor access bit is off 0B67 3E 10 ld a,loop ;clear the shift register 0B69 D3 4C out (mcr),a ; - by looping back. 0B6B DB 48 in a,(rbr) ;clear receiver buffer 0B6D AF xor a 0B6E D3 48 out (thr),a ;clear transmitter buffer 0B70 CD 0B9E call begin0 0B73 DB 48 in a,(rbr) 0B75 AF xor a 0B76 D3 48 out (thr),a 0B78 CD 0B9E call begin0 ;two times to make sure 0B7B DB 4D rduart: in a,(lsr) 0B7D E6 01 and dr ;check for data available 0B7F 28 FA jr z,rduart 0B81 DB 48 in a,(rbr) ;intitialize receiver buffer 0B83 FE 00 cp 0 0B85 28 0F jr z,contin ;jump if UARTS good 0B87 F5 urterr: push af 0B88 3E 55 ld a,'U' 0B8A 32 0016 ld (ersav),a ;Uart error 0B8D 7A ld a,d 0B8E 32 0018 ld (ersav + 2),a ;Uart # saved 0B91 F1 pop af 0B92 32 0017 ld (ersav + 1),a ;bad character saved 0B95 AF xor a 0B96 D3 4C contin: out (mcr),a 0B98 7A ld a,d 0B99 FE 03 cp 3 ;initialize all three uarts 0B9B C8 ret z 0B9C 18 B7 jr setit 0B9E DB 4D begin0: in a,(lsr) 0BA0 E6 20 and thre 0BA2 28 FA jr z,begin0 0BA4 C9 ret ; Baud rate selection table for Mult I/o or WB I/O 0BA5 0417 btable: dw 1047 ;110 baud 0 0 0 0BA7 0180 dw 384 ;300 baud 0 0 1 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-21 '(c) 1981 Morrow Designs' 0BA9 0060 dw 96 ;1200 baud 0 1 0 0BAB 0030 dw 48 ;2400 baud 0 1 1 0BAD 0018 dw 24 ;4800 baud 1 0 0 0BAF 000C dw 12 ;9600 baud 1 0 1 0BB1 0006 dw 6 ;19200 baud 1 1 0 ; Load constants command for the DMA Winchester controller 0BB3 10 bootbl: db 10h ;direction --> track 0 0BB4 00 db 0 ;low steps 0BB5 00 db 0 ;high steps 0BB6 3C db 03ch ;select drive 0 0BB7 00 db 0 ;low dma address 0BB8 01 db 01 ;high dma address 0BB9 00 db 0 ;extended dma address 0BBA 00 db 0 ;argument 0 0BBB 1E db stpdly ;argument 1 0BBC C8 db hdsetl ;argument 2 0BBD 03 db secsiz ;argument 3 0BBE 04 db const ;load constants opcode 0BBF 00 db 0 ;clear status byte 0BC0 80 db 80h ;low link address 0BC1 00 db 0 ;high link address 0BC2 00 db 0 ;extended link address 0BC3 endboot equ $ ; Read sector 1, head 0, cyl 0 command for the HD-DMA: 0BC3 00 rdtbl: db 0 ;no seek 0BC4 00 db 0 0BC5 00 db 0 0BC6 7C db 07ch ;select drive 0, head 0 0BC7 00 db 0 ;dma address of 100h 0BC8 01 db 1 0BC9 00 db 0 0BCA 00 db 0 ;low byte cylinder 0BCB 00 db 0 ;high byte cylinder 0BCC 00 db 0 ;head 0 0BCD 00 db 0 ;sector 1 0BCE 00 db 0 ;read command 0BCF 00 db 0 ;clear status 0BD0 endrd equ $ 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-22 '(c) 1981 Morrow Designs' ; Dispatch table for the on-board diagnostic routines 0BD0 jtable equ $ 0BD0 C3 0800 jp regrd ;test all the readable registers 0BD3 00 db 0 0BD4 C3 080E jp regwr ;check all the writable registers but ; -task register 0BD7 00 db 0 0BD8 C3 0821 jp tmap ;check map rams 0BDB 00 db 0 0BDC C3 083A jp tram ;check read/write ram 0BDF 00 db 0 0BE0 C3 084E jp tfpp ;check fpp 0BE3 00 db 0 0BE4 C3 0876 jp tbus ;check bus read/write addresses 0BE7 00 db 0 0BE8 C3 08A3 jp ntbus ;R/W bus with 055h and 0aah 0BEB 00 db 0 0BEC 18 0B jr start ;yet to be defined 0BEE ecode0 equ $ ;End of reset prom code 0BEE ds 3f0h-(ecode0-rom0) ;Fill out the prom ;**************************************************************** ;* * ;* The following special piece of code is where the user task * ;* begins executing when a reset trap occurs. * ;* * ;**************************************************************** 0BF0 21 104A ld hl,djstat 0BF3 3E 00 ld a,0h 0BF5 32 0602 ld (mapram + 2),a ;t0 map points to t1 map seg 0 0BF8 3C inc a 0BF9 31 0200 start: ld sp,map 0BFC C3 085A jp getsw ;power-on or reset jump 0BFF 00 nop ;Fill out the prom. 0C00 erom0 equ $ 0C00 ds 400h-(erom0-rom0) .phase 800h 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-23 '(c) 1981 Morrow Designs' ;**************************************************************** ;* * ;* This code is usuable by the supervisor task (task0) * ;* but is not accessible to any other tasks. Any trap * ;* other than a reset will enable this half of the eprom * ;* as well. * ;* * ;**************************************************************** 0800 rom1 equ $ ;**************************************************************** ;* * ;* ===>> J U M P T A B L E <<=== * ;* * ;**************************************************************** 0800 C3 0821 svtrap: jp trappd ;trap routine, check out reason why 0803 C3 0812 tskbse: jp what ;vestigial 0806 C3 08E6 nmap: jp putmap ;set up new allocation vector, access 0809 C3 089D gotsk: jp gotask ;switch to new task 080C C3 08D9 getmap: jp gtmap ;get the old allocation vector, access 080F C3 0812 dupmap: jp what ;vestigial 0812 C3 08F9 what: jp monitor ;debugger/monitor called 'MON' 0815 C3 0892 restr: jp restor ;restore task 0 map to normal condition 0818 oldtask: 0818 C3 0809 jp gotsk ;jumps to last task before trap 081B C3 0885 wrtask: jp writsk ;writes value in CTASK to task register 081E C3 0888 wratsk: jp atask ;writes value in 'A' to task register 0821 11 FFF1 trappd: ld de,-15 ;back up the users pc 0824 E1 pop hl 0825 19 add hl,de 0826 22 000C ld (u.pc),hl 0829 3A 0006 ld a,(ctask) 082C FE 00 cp 0 082E CA 0872 jp z,suptrap 0831 D1 pop de 0832 E1 pop hl 0833 F1 pop Af 0834 ED 7B 0008 ld sp,(cstack) ;set up reg_save stack in supervisor 0838 08 alltrp: ex Af,Af' ;save user's auxiliary registers 0839 D9 exx 083A E5 push hl 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-24 '(c) 1981 Morrow Designs' 083B D5 push de 083C C5 push bc 083D F5 push Af 083E FD E5 push iy 0840 DD E5 push ix 0842 ED 57 ld a,i ;get interupt register 0844 F5 push af ;save it 0845 08 ex Af',Af 0846 D9 exx 0847 E5 push hl ;- and save all user registers 0848 D5 push de 0849 C5 push bc 084A F5 push Af 084B 2A 0006 ld hl,(ctask) ;save the task and mask 084E ED 5B 000A ld de,(u.sp) ;get the user's stack pointer 0852 ED 4B 000C ld bc,(u.pc) 0856 D5 push de ;save the user's stack pointer 0857 C5 push bc ;save the user's program counter 0858 E5 push hl ;save the current task and mask 0859 ED 73 0014 ld (regsav),sp ;beginning address of reg save area ; - saved here. ;Stop switch calls the monitor - return will restore to "CTASK" 085D 7D ld a,l ;get the trapped task # 085E FE 00 cp 0 0860 28 07 jr z,gowhat ;if trap was in task 0, go to monitor 0862 3A 0403 ld a,(stats) 0865 CB 67 bit 4,a 0867 20 13 jr nz,gosupr ;go to super unless it was a stop trap 0869 AF gowhat: xor a 086A 32 0006 ld (ctask),a 086D CD 0812 call what 0870 18 2B jr gotask 0872 suptrap: 0872 D1 pop de 0873 E1 pop hl 0874 F1 pop Af 0875 ED 7B 000A ld sp,(u.sp) 0879 C3 0838 jp alltrp ;Call the supervisor - a return will restore the task in "CTASK" 087C AF gosupr: xor a 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-25 '(c) 1981 Morrow Designs' 087D 32 0006 ld (ctask),a 0880 CD 0000 call super 0883 18 18 jr gotask ;******************************************************** ;* * ;* Writsk will take the value in CTASK and write it * ;* to the TASK register. It then waits 6 instructions * ;* for the hardware delay and returns with traps set * ;* and operation in the task selected. The 'A' re- * ;* gister is not preserved, all others untouched. * ;* * ;******************************************************** 0885 3A 0006 writsk: ld a,(ctask) 0888 32 0402 atask: ld (task),a ;update the task register and count 088B 00 nop ; - 7 instructions to delay for the 088C 00 nop ; - hardware swap counter. 088D 00 nop 088E 00 nop 088F 00 nop 0890 00 nop 0891 C9 ret ;******************************************************** ;* * ;* Restore will restore Task 0's map with its old * ;* values. This assumes that if the map for task 0 * ;* has been changed, that only the actual map had * ;* been changed and that the image map was left in * ;* the condition before the change occurred. * ;* * ;******************************************************** 0892 21 0200 restor: ld hl,map ;point to beginning of map image 0895 11 0600 ld de,mapram ;point to beginning of actual map 0898 01 001F ld bc,01Fh ;all of task 0 map 089B ED B0 ldir ;**************************************************************** ;* * ;* Gotask restores all the task's registers and then * ;* switches to that task. * 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-26 '(c) 1981 Morrow Designs' ;* * ;**************************************************************** 089D 21 0000 gotask: ld hl,0 ;init hl for normal entry 08A0 39 add hl,sp 08A1 F9 ntask: ld sp,hl 08A2 E1 pop hl 08A3 22 0006 ld (ctask),hl ;get back CTASK and CMASK 08A6 E1 pop hl 08A7 22 000C ld (u.pc),hl ;get back the user's pc 08AA E1 pop hl 08AB 22 000A ld (u.sp),hl ;get back the user's sp 08AE F1 pop Af ;get back the primary registers 08AF C1 pop bc 08B0 D1 pop de 08B1 E1 pop hl 08B2 08 ex Af',Af 08B3 D9 exx 08B4 F1 pop Af ;get back the interrupt register 08B5 ED 47 ld i,a ;restore it 08B7 DD E1 pop ix ;restore auxilliary registers 08B9 FD E1 pop iy 08BB 2A 000C ld hl,(u.pc) 08BE 22 0004 bcomnd: ld (user + 1),hl ;form jump to user's pc value @ user 08C1 3E C3 ld a,jmpop 08C3 32 0003 ld (user),a 08C6 F1 pop Af ;restore the alternate registers 08C7 C1 pop bc 08C8 D1 pop de 08C9 2A 0006 ld hl,(ctask) 08CC 22 0402 ld (task),hl ;write the new task and mask 08CF E1 pop hl 08D0 08 ex Af,Af' 08D1 D9 exx 08D2 ED 7B 000A ld sp,(u.sp) 08D6 C3 0003 jp user ;******************************************************** ;* * ;* The following code will return with: * ;* Register A = task #/ segment # * ;* Register B = old allocation vector * ;* Register C = old access priviledges * ;* Upon entry, it expects the A register to have * ;* the desired task# / segment #. Consider this to be * 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-27 '(c) 1981 Morrow Designs' ;* opposite of the putmap routine. * ;* * ;******************************************************** 08D9 6F gtmap: ld l,a ;get task and segment numbers 08DA 26 00 ld h,0h 08DC 29 add hl,hl ;multiply times 2 08DD EB ex de,hl ;save calculated offset in de 08DE 21 0200 ld hl,map ;point to beginning of map ram image 08E1 19 add hl,de ;add offset to get desired map 08E2 46 ld b,(HL) ;get old allocation vector 08E3 23 inc hl ;offset to access map 08E4 4E ld c,(HL) ;get old access priviledges 08E5 C9 ret ;******************************************************** ;* * ;* Putmap updates a task's allocation vectors and * ;* access atributes. Upon entry, registers must * ;* contain: * ;* a = task # / task segment # to update * ;* high nibble = task#, low nibble = segment# * ;* b = new allocation vector * ;* c = new access privilidges * ;* * ;* Routine calculates the expression 600 + (a) X 2 * ;* where a is as listed above. All arithmetic and * ;* numbers are in Hex. * ;* * ;******************************************************** 08E6 6F putmap: ld l,a ;get task and segment number 08E7 26 00 ld h,0h ; 08E9 29 add hl,hl ;multiply times 2 08EA EB ex de,hl ;save calculated offset in de 08EB 21 0600 ld hl,mapram ;point to beginning of ram map 08EE CD 08F4 call putmxx 08F1 21 0200 ld hl,map ;point to beginning of image map 08F4 19 putmxx: add hl,de ;add offset to selected map 08F5 70 ld (hl),b ;write the allocation vector 08F6 23 inc hl ;point to access attribute ram 08F7 71 ld (hl),c ;write new access atributes 08F8 C9 ret 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-28 '(c) 1981 Morrow Designs' ;******************************************************** ;* * ;* The following routines make up the debugging tool * ;* monitor * ;* * ;******************************************************** 08F9 monitor: 08F9 ED 73 0030 ld (monstk -2),sp ;save stack for 'u' & 'c' commands 08FD FD 2A 0030 ld iy,(monstk-2) 0901 31 0032 ld sp,monstk 0904 2A 0014 ld hl,(regsav) ;get the stack location 0907 11 001B ld de,27 ;number of saved registers 090A E5 push hl 090B 19 add hl,de 090C EB ex de,hl 090D E1 pop hl 090E 01 0922 ld bc,ustart 0911 C5 push bc 0912 C3 0949 jp udi0 ;print out the registers 0915 3A 0016 cold: ld a,(ersav) ;retrieve the error byte if any 0918 4F ld c,a 0919 CD 0A38 call ucout1 ;print it 091C 2A 0017 ld hl,(ersav + 1) ;retrieve disk command 091F CD 0AC7 call uladr 0922 31 0032 ustart: ld sp,monstk 0925 11 0922 LD DE,USTART 0928 D5 PUSH DE 0929 CD 0A05 CALL UCRLF 092C 0E 3A LD C,':' 092E CD 0A38 CALL ucout1 0931 CD 0B08 USTAR0: CALL UTI 0934 B7 OR A 0935 28 FA JR Z,USTAR0 0937 FE 7B CP 'z'+1 0939 D2 0A24 JP NC,UERROR 093C 0E 02 LD C,002H 093E FE 44 CP 'D' 0940 28 04 JR Z,udisp 0942 FE 64 cp 'd' 0944 20 19 jr nz,ufill ; ; DISPLAY MEMORY XXXX TO XXXX 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-29 '(c) 1981 Morrow Designs' ; ; 0946 CD 0A00 UDISP: CALL UEXLF 0949 CD 0A05 UDI0: CALL UCRLF 094C CD 0AC7 CALL ULADR 094F 06 10 LD B,010H 0951 CD 0A36 UDI1: CALL UBLK 0954 7E LD A,(HL) 0955 CD 0ACC CALL ULBYTE 0958 CD 0AA3 CALL UHILOX 095B 10 F4 DJNZ UDI1 095D 18 EA JR UDI0 ; ; ; ; FILL MEMORY XXXX TO XXXX WITH XX ; ; ; 095F FE 46 UFILL: CP 'F' 0961 28 04 JR z,ufill0 0963 FE 66 cp 'f' 0965 20 0D jr nz,ugoto 0967 CD 0A71 ufill0: CALL UEXPR3 096A 71 UFI0: LD (HL),C 096B CD 0AA9 CALL UHILO 096E 30 FA JR NC,UFI0 0970 D1 POP DE 0971 C3 0922 JP USTART ; ; ; GOTO (EXECUTE) XXXX ; ; 0974 FE 47 UGOTO: CP 'G' 0976 28 04 JR Z,ugoto0 0978 FE 67 cp 'g' 097A 20 08 jr nz,umtest 097C CD 0A7C ugoto0: CALL UEXPR1 097F CD 0A05 CALL UCRLF 0982 E1 POP HL 0983 E9 JP (HL) ; ; ; TEST MEMORY XXXX TO XXXX ; 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-30 '(c) 1981 Morrow Designs' ; 0984 FE 54 UMTEST: CP 'T' 0986 28 04 JR Z,ut10 0988 FE 74 cp 't' 098A 20 1C jr nz,umove 098C CD 0A00 ut10: CALL UEXLF 098F 7E UT1: LD A,(HL) 0990 47 LD B,A 0991 2F CPL 0992 77 LD (HL),A 0993 AE XOR (HL) 0994 28 0C JR Z,UT2 0996 D5 PUSH DE 0997 5F LD E,A 0998 CD 0A33 CALL UHLSP 099B CD 0B3F CALL UQI1 099E CD 0A05 CALL UCRLF 09A1 D1 POP DE 09A2 70 UT2: LD (HL),B 09A3 CD 0AA3 CALL UHILOX 09A6 18 E7 JR UT1 ; ; ; MOVE DATA FROM XXXX TO XXXX ; ; 09A8 FE 4D UMOVE: CP 'M' 09AA 28 04 JR Z,umvo0 09AC FE 6D cp 'm' 09AE 20 12 jr nz,usubs 09B0 CD 0A71 umvo0: CALL UEXPR3 09B3 7E UMV0: LD A,(HL) 09B4 02 LD (BC),A 09B5 03 INC BC 09B6 CD 0AA3 CALL UHILOX 09B9 18 F8 JR UMV0 09BB DD 77 00 USTORE: LD (IX+00H),A 09BE DD 23 INC IX 09C0 1D DEC E 09C1 C9 RET ; ; ; EXAMINE AND/OR REPLACE MEMORY DATA ; ; 09C2 FE 53 USUBS: CP 'S' 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-31 '(c) 1981 Morrow Designs' 09C4 CA 09CC JP Z,usuo0 09C7 FE 73 cp 's' 09C9 C2 0AB3 jp nz,uhexn 09CC CD 0A7C usuo0: CALL UEXPR1 09CF CD 0AFC CALL UQCHK 09D2 DA 0A24 JP C,UERROR 09D5 E1 POP HL 09D6 7E USU0: LD A,(HL) 09D7 CD 0ACC CALL ULBYTE 09DA 0E 2D LD C,02DH 09DC CD 0AF6 CALL UCOPCK 09DF D8 RET C 09E0 28 10 JR Z,USU1 09E2 E5 PUSH HL 09E3 21 0000 LD HL,0 09E6 0E 01 LD C,001H 09E8 CD 0A84 CALL UEX1 09EB D1 POP DE 09EC E1 POP HL 09ED 73 LD (HL),E 09EE 78 LD A,B 09EF FE 0D CP 00DH 09F1 C8 RET Z 09F2 23 USU1: INC HL 09F3 CD 0A05 CALL UCRLF 09F6 E5 PUSH HL 09F7 CD 0AC7 CALL ULADR 09FA CD 0A36 CALL UBLK 09FD E1 POP HL 09FE 18 D6 JR USU0 ; ; 0A00 CD 0A7E UEXLF: CALL UEXPR 0A03 D1 POP DE 0A04 E1 POP HL ; CR/LF OUTPUT ; ; 0A05 E5 UCRLF: PUSH HL 0A06 C5 PUSH BC 0A07 0E 0D LD C,0DH 0A09 CD 0A38 CALL ucout1 0A0C 0E 0A LD C,0AH 0A0E CD 0A38 CALL ucout1 0A11 C1 POP BC 0A12 E1 POP HL 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-32 '(c) 1981 Morrow Designs' 0A13 CD 0A53 CALL UCSTS 0A16 B7 OR A 0A17 C8 RET Z ; ; CHECK FOR CONTROL CHARACTER ; ; 0A18 CD 0A45 UCCHK: CALL ucon1 0A1B E6 7F AND 07FH 0A1D FE 13 CP 013H ;CONTROL-S 0A1F 28 F7 JR Z,UCCHK 0A21 FE 03 CP 003H ;CONTROL-C 0A23 C0 RET NZ 0A24 CD 0ADB UERROR: CALL UMEMSIZ 0A27 11 0A24 LD DE,UERROR 0A2A D5 PUSH DE 0A2B 0E 3F LD C,'?' 0A2D CD 0A38 CALL ucout1 0A30 C3 0922 JP USTART 0A33 CD 0AC7 UHLSP: CALL ULADR ; ; PRINT SPACE CHARACTER ; 0A36 0E 20 UBLK: LD C,020H ;******************************************************** ;* * ;* Console I/O routines for the Wunderbus I/O. These * ;* routines assume that the uart divisor latch has * ;* previously set (either on power up or in routine * ;* executed before a trap to this routine occurred. * ;* The character to output should be in the 'C' reg- * ;* ister, the character received is returned in the * ;* 'A' register. UCSTS returns with zero flag set * ;* when no character is waiting in the UART buffer, * ;* or with A = FFh if a character is waiting. * ;* * ;******************************************************** 0A38 CD 0A5E ucout1: call uconinit 0A3B DB 4D ucout2: in a,(lsr) ;get uart status 0A3D E6 20 and thre 0A3F 28 FA jr z,ucout2 ;loop until tbe 0A41 79 ld a,c 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-33 '(c) 1981 Morrow Designs' 0A42 D3 48 out (thr),a ;output the data to uart 0A44 C9 ret 0A45 CD 0A5E ucon1: call uconinit 0A48 DB 4D ucon2: in a,(lsr) ;get uart status 0A4A E6 01 and dr 0A4C 28 FA jr z,ucon2 ;wait until receive data available 0A4E DB 48 in a,(rbr) ;read the uart data register 0A50 E6 7F and 07fh ;strip parity 0A52 C9 ret 0A53 CD 0A5E ucsts: call uconinit 0A56 DB 4D in a,(lsr) ;read uart status 0A58 E6 01 and dr 0A5A C8 ret z ;return zero set if no character 0A5B 3E FF ld a,0ffh 0A5D C9 ret ;return a = ffh if character waiting 0A5E uconinit: 0A5E 3E 09 ld a,group1 0A60 D3 4F out (grpctl),a ;set up for UART 1 0A62 3E 07 ld a,wls0+wls1+stb 0A64 D3 4B out (lcr),a ;8 bit word, 2 bit stop bits 0A66 C9 ret ; CONVERT HEX TO ASCII 0A67 E6 0F UCONV: AND 00fh 0A69 C6 90 ADD A,090H 0A6B 27 DAA 0A6C CE 40 ADC A,040H 0A6E 27 DAA 0A6F 4F LD C,A 0A70 C9 RET ; ; GET PARAMETERS 1,2,OR 3 ; 0A71 0C UEXPR3: INC C 0A72 CD 0A7E CALL UEXPR 0A75 CD 0A05 CALL UCRLF 0A78 C1 POP BC 0A79 D1 POP DE 0A7A E1 POP HL 0A7B C9 RET 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-34 '(c) 1981 Morrow Designs' 0A7C 0E 01 UEXPR1: LD C,001H 0A7E 21 0000 UEXPR: LD HL,0 0A81 CD 0B08 UEX0: CALL UTI 0A84 47 UEX1: LD B,A 0A85 CD 0ADC CALL UNIBBLE 0A88 38 08 JR C,UEX2 0A8A 29 ADD HL,HL 0A8B 29 ADD HL,HL 0A8C 29 ADD HL,HL 0A8D 29 ADD HL,HL 0A8E B5 OR L 0A8F 6F LD L,A 0A90 18 EF JR UEX0 0A92 E3 UEX2: EX (SP),HL 0A93 E5 PUSH HL 0A94 78 LD A,B 0A95 CD 0AFC CALL UQCHK 0A98 30 02 JR NC,UEX3 0A9A 0D DEC C 0A9B C8 RET Z 0A9C C2 0A24 UEX3: JP NZ,UERROR 0A9F 0D DEC C 0AA0 20 DC JR NZ,UEXPR 0AA2 C9 RET 0AA3 CD 0AA9 UHILOX: CALL UHILO 0AA6 D0 RET NC 0AA7 D1 POP DE 0AA8 C9 RET 0AA9 23 UHILO: INC HL 0AAA 7C LD A,H 0AAB B5 OR L 0AAC 37 SCF 0AAD C8 RET Z 0AAE 7B LD A,E 0AAF 95 SUB L 0AB0 7A LD A,D 0AB1 9C SBC A,H 0AB2 C9 RET ; ; HEXADECIMAL ARITHMETIC ; 0AB3 FE 48 UHEXN: CP 'H' 0AB5 28 04 JR Z,uhexd 0AB7 FE 68 cp 'h' 0AB9 20 67 jr nz,uport 0ABB CD 0A00 uhexd: CALL UEXLF 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-35 '(c) 1981 Morrow Designs' 0ABE E5 PUSH HL 0ABF 19 ADD HL,DE 0AC0 CD 0A33 CALL UHLSP 0AC3 E1 POP HL 0AC4 B7 OR A 0AC5 ED 52 SBC HL,DE ; ; CONVERT HL REGISTER TO ASCII ; 0AC7 7C ULADR: LD A,H 0AC8 CD 0ACC CALL ULBYTE 0ACB 7D LD A,L ; ; CONVERT A REGISTER TO ASCII ; 0ACC F5 ULBYTE: PUSH AF 0ACD 0F RRCA 0ACE 0F RRCA 0ACF 0F RRCA 0AD0 0F RRCA 0AD1 CD 0AD5 CALL UDBLC 0AD4 F1 POP AF 0AD5 CD 0A67 UDBLC: CALL UCONV 0AD8 C3 0A38 JP ucout1 ;checked 0ADB UMEMSIZ: 0ADB C9 RET 0ADC UNIBBLE: 0ADC FE 61 cp 'a' ;is it less than lower case 'a'? 0ADE 38 06 jr c,unibok ;take jump if so 0AE0 FE 7B cp 'z'+1 ;less than a lower case 'z'? 0AE2 3F ccf ;set carry and return if > 'z' 0AE3 D8 ret c 0AE4 D6 20 sub ' ' ;convert to upper case 0AE6 D6 30 unibok: SUB 030H 0AE8 D8 RET C 0AE9 FE 17 cp 017h 0AEB 3F ccf 0AEC D8 RET C 0AED FE 0A CP 00AH 0AEF 3F CCF 0AF0 D0 RET NC 0AF1 D6 07 SUB 007H 0AF3 FE 0A CP 00AH 0AF5 C9 RET 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-36 '(c) 1981 Morrow Designs' 0AF6 CD 0A38 UCOPCK: CALL ucout1 0AF9 CD 0B08 UPCHK: CALL UTI ; ; CHARACTER CHECK ; 0AFC FE 20 UQCHK: CP 020H 0AFE C8 RET Z 0AFF FE 2C CP 02CH 0B01 C8 RET Z 0B02 FE 0D CP 00DH 0B04 37 SCF 0B05 C8 RET Z 0B06 3F CCF 0B07 C9 RET ; ; ECHO CONSOLE ; 0B08 CD 0A45 UTI: CALL ucon1 0B0B 3C INC A 0B0C C8 RET Z 0B0D 3D DEC A 0B0E E6 7F AND 07FH 0B10 C8 RET Z 0B11 FE 00 CP 000H 0B13 C8 RET Z 0B14 FE 4E CP 04EH 0B16 C8 RET Z 0B17 FE 6E CP 06EH 0B19 C8 RET Z 0B1A C5 PUSH BC 0B1B 4F LD C,A 0B1C CD 0A38 CALL ucout1 0B1F 79 LD A,C 0B20 C1 POP BC 0B21 C9 RET ; ; READ/WRITE TO I/O PORT ; 0B22 FE 4F UPORT: CP 'O' 0B24 28 2A JR Z,UQOUT 0B26 FE 6F CP 'o' 0B28 28 26 jr z,uqout 0B2A FE 49 CP 'I' 0B2C 28 06 JR Z,uin 0B2E FE 69 cp 'i' 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-37 '(c) 1981 Morrow Designs' 0B30 28 02 jr z,uin 0B32 18 24 JR UVERIFY 0B34 CD 0A7C UIN: CALL UEXPR1 0B37 0E 0A LD C,0AH 0B39 CD 0A38 CALL ucout1 0B3C C1 POP BC 0B3D ED 58 UQ0: IN E,(C) 0B3F 06 08 UQI1: LD B,008H 0B41 CD 0A36 CALL UBLK 0B44 CB 23 UQI2: SLA E 0B46 3E 18 LD A,018H 0B48 8F ADC A,A 0B49 4F LD C,A 0B4A CD 0A38 CALL ucout1 0B4D 10 F5 DJNZ UQI2 0B4F C9 RET 0B50 CD 0A7E UQOUT: CALL UEXPR 0B53 D1 POP DE 0B54 C1 POP BC 0B55 ED 59 OUT (C),E 0B57 C9 RET ; ; ; ; ; VERIFY MEMORY XXXX TO XXXX WITH XXXX ; 0B58 UVERIFY: 0B58 FE 56 CP 'V' 0B5A 28 04 JR Z,uver0 0B5C FE 76 cp 'v' 0B5E 20 12 jr nz,uretrn 0B60 CD 0A71 uver0: call uexpr3 0B63 0A UVERIO: LD A,(BC) 0B64 BE CP (HL) 0B65 28 05 JR Z,U..B 0B67 C5 PUSH BC 0B68 CD 0BC8 CALL UCERR 0B6B C1 POP BC 0B6C 03 U..B: INC BC 0B6D CD 0AA3 CALL UHILOX 0B70 18 F1 JR UVERIO ; Return to task which just trapped with old pc and registers restored 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-38 '(c) 1981 Morrow Designs' ; All registers are saved!! 0B72 FE 43 uretrn: cp 'C' 0B74 28 04 jr z,uretr1 0B76 FE 63 cp 'c' 0B78 20 0B jr nz,ucontr 0B7A FD F9 uretr1: ld sp,iy ;get back the user save stack 0B7C D1 pop de ; ... the return address 0B7D E1 pop hl ; ... Ctask/Cmask 0B7E 7C ld a,h 0B7F F6 08 or 08h ;set the run bit for 'run' 0B81 67 ld h,a 0B82 E5 push hl ;restore the stack 0B83 D5 push de 0B84 C9 ret ;return to user through 'gotask' ; Return to trapped task, execute next instruction and trap back ; All registers are saved but the mask is changed!! 0B85 FE 55 ucontr: cp 'U' 0B87 28 04 jr z,ucont1 0B89 FE 75 cp 'u' 0B8B 20 0B jr nz,uboot 0B8D FD F9 ucont1: ld sp,iy ;get back the user save stack 0B8F D1 pop de ;... the return address 0B90 E1 pop hl ;... CTASK/CMASK 0B91 7C ld a,h 0B92 E6 F6 and 0f6h ;force mask for stop and run enble low 0B94 67 ld h,a 0B95 E5 push hl ;restore the stack 0B96 D5 push de 0B97 C9 ret ;return to user through 'gotask' ; Jump to the cpu switch address into task specified by CTASK ; No registers are preserved!! 0B98 FE 42 uboot: cp 'B' 0B9A 28 05 jr z,uboot1 0B9C FE 62 cp 'b' 0B9E C2 0A24 jp nz,uerror 0BA1 08 uboot1: ex Af',Af 0BA2 D9 exx 0BA3 AF xor a 0BA4 3C inc a 0BA5 32 0602 ld (mapram + 2),a ;restore the actual map 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-39 '(c) 1981 Morrow Designs' 0BA8 32 0202 ld (map + 2),a ;restore map image 0BAB 3A 0402 ld a,(switch) 0BAE E6 F8 and 0f8h 0BB0 FE 00 cp 0 ;HDCA Boot? 0BB2 28 0E jr z,uboot2 0BB4 FE 08 cp 8 ;HD-DMA Boot? 0BB6 28 0A jr z,uboot2 0BB8 FE 10 cp 10h ;DJ-DMA Boot? 0BBA 28 06 jr z,uboot2 0BBC 67 ld h,a ;Memory Address jump 0BBD 2E 00 ld l,0 0BBF C3 08BE jp bcomnd 0BC2 2A 000C uboot2: ld hl,(u.pc) ;get the boot address for controllers 0BC5 C3 08BE jp bcomnd ; MEMORY MISMATCH PRINTOUT ; 0BC8 47 UCERR: LD B,A 0BC9 CD 0A33 CALL UHLSP 0BCC 7E LD A,(HL) 0BCD CD 0ACC CALL ULBYTE 0BD0 CD 0A36 CALL UBLK 0BD3 78 LD A,B 0BD4 CD 0ACC CALL ULBYTE 0BD7 C3 0A05 JP UCRLF 0BDA ecode1 equ $ 0BDA ds 3eeh - (ecode1-rom1) 0BEE FFFF serial: dw 0ffffh ;Micronix serialization word ;******************************************************** ;* * ;* The following piece of code is where the user * ;* task begins execution whenever a trap occurs. * ;* The users registers and sp are saved in the * ;* temporary users store area. * ;* * ;******************************************************** 0BF0 00 nop ;must be nop to void a halt 0BF1 ED 73 000A ld (u.sp),sp ;save the users stack pointer 0BF5 31 0014 ld sp,begsave ;set sp to the temporary save area 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE 1-40 '(c) 1981 Morrow Designs' 0BF8 F5 push af 0BF9 E5 push hl 0BFA D5 push de 0BFB 00 nop 0BFC CD 0821 call trappd ;go to supervisor trap via temp 0BFF 76 halt ;halt here allows T0 to halt 0C00 erom1 equ $ 0C00 ds 400h-(erom1-rom1) 0C00 fpp0: ds 8 0C08 fpp1: ds 1 end 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE S '(c) 1981 Morrow Designs' Macros: Symbols: ACR 000D ADI4 0004 ADI8 0000 AFF 000C AFOFST 0015 ALF 000A ALLERR 0A6B ALLTRP 0838 ARG 1087 ASP 0020 ATASK 0888 ATTN 0055 BADRAM 0949 BASE 0048 BCOFST 000F BCOMND 08BE BEGIN0 0B9E BEGSAV 0014 BEL 0007 BOOTAD 1100 BOOTBL 0BB3 BOOTHD 0AA3 BSP 0008 BTABLE 0BA5 CALLOP 00CD CHAN 1080 CHECK 096D CLOOP 0A3E CLOOP0 0A40 CLOOP1 0A45 CLOOP2 0A5A CMASK 0007 CMMD 108B COLD 0915 COMMD 0051 COMPLT 0004 CONST 0004 CONTIN 0B96 CONTRL 0050 CSTACK 0008 CTASK 0006 CYL 0099 DATA 0053 DEFAUL 0B52 DEOFST 0011 DERROR 0A62 DJDMA 09C9 DJLOOP 09CE DJLOP0 09CB DJSTAT 104A DLAB 0080 DLL 0048 DLM 0049 DMADDR 1084 DMARST 0054 DR 0001 DREAD 0001 DREADY 0004 DRENBL 0005 DRIVEA 00FC DSKRUN 0007 DSPCOL 0401 DSPSEG 0400 DUPMAP 080F DXLOOP 0B10 ECODE0 0BEE ECODE1 0BDA ELOCIO 0404 ENDBOO 0BC3 ENDRD 0BD0 EOI 0020 EROM0 0C00 EROM1 0C00 ERSAV 0016 FMAP 0913 FORMAT 0003 FPP0 0C00 FPP1 0C08 FUNCTN 0052 GETMAP 080C GETSW 085A GOBUFF 01B0 GOOD 00FF GOSUPR 087C GOTASK 089D GOTSK 0809 GOWHAT 0869 GROUP0 0008 GROUP1 0009 GROUP2 000A GROUP3 000B GRPCTL 004F GTMAP 08D9 HDCERR 0A99 HDCLOP 0A79 HDLOP1 0A7C HDRL 0A11 HDSETL 00C8 HDSPT 0011 HEADER 0008 HEADS 0004 HIVECT 0000 HLOFST 0013 HOME 0A17 HSTRAP 001A IC4 0001 ICW1 004C ICW2 004D ICW3 004D ICW4 004D IER 0049 IMASK 0000 INIT 0010 IOADDR 0050 IOPB 1050 IWAIT1 0ACB IWAIT2 0AD0 IWAIT3 0AD5 JMPOP 00C3 JTABLE 0BD0 KEYBD 0401 LCR 004B LINK 108D LLOOP 0B03 LOCIO 0400 LOOP 0010 LOVECT 0000 LSR 004D LTIM 0008 MAP 0200 MAPRAM 0600 MASK 0403 MCR 004C MONITO 08F9 MONSTK 0032 MONTOR 0982 MSKOFS 0019 NEXCHK 093E NMAP 0806 NOOP 0006 NOP 0000 NORMAL 0000 NSTAT 09F1 NTASK 08A1 NTBUS 08A3 NUBOOT 09F7 NUTASK 0986 NXTBYT 0076 OCW1 004D OCW2 004C OLDTAS 0818 OPDONE 0002 PCOFST 000D PICMAS 00FF PICSET 09AF PUTMAP 08E6 PUTMXX 08F4 RAM 0000 RAMCHK 0932 RBR 0048 RDATA 0A2A RDTBL 0BC3 RDUART 0B7B READAT 0000 READY 0020 REGRD 0800 REGSAV 0014 REGWR 080E REGWR1 080F RESET 085F RESET0 08D8 RESET1 08E4 RESLOP 08FA RESLP1 090A RESLP2 08FD RESTOR 0892 RESTR 0815 RETSTK 01E2 REVNUM 000D RHEAD 0002 RLOOP 0AAB ROM0 0800 ROM1 0800 RSTMAP 0B18 'MPZ-80 MON4.45-M FIRMWARE' MACRO-80 3.36 17-Mar-80 PAGE S-1 '(c) 1981 Morrow Designs' RSTMXX 0B26 SDONE 0AC8 SECSIZ 0003 SECSTA 0051 SECTOR 0001 SEKCMP 0008 SELECT 1083 SENSE 0005 SERIAL 0BEE SETIT 0B55 SETTLE 08E7 SETUP 091D SNGL 0002 SPOFST 0017 SSMODE 0036 START 0BF9 STATIS 108C STATS 0403 STATUS 0050 STB 0004 STEPIN 0000 STEPO 00F8 STEPOU 0010 STPDLY 001E SUPER 0000 SUPTRA 0872 SVTRAP 0800 SWITCH 0402 SYSTEM 0080 T.AF 01EA T.AF1 01F8 T.BC 01EC T.BC1 01FA T.DE 01EE T.DE1 01FC T.HL 01F0 T.HL1 01FE T.INT 01F2 T.IX 01F4 T.IY 01F6 T.PC 01E6 T.SP 01E8 T0MASK 002B T1MASK 002B TASK 0402 TBUS 0876 TEMPST 0200 TFPP 084E THR 0048 THRE 0020 TMAP 0821 TRACK0 0001 TRAM 083A TRAM1 083F TRAPPD 0821 TRK0 0001 TRPADD 0400 TSKBSE 0803 TSKMSK 01E4 TSTSW 0957 U..B 0B6C U.AF 0012 U.DE 000E U.HL 0010 U.PC 000C U.SP 000A UARTS0 0B2D UARTST 0B2B UBLK 0A36 UBOOT 0B98 UBOOT1 0BA1 UBOOT2 0BC2 UCCHK 0A18 UCERR 0BC8 UCON1 0A45 UCON2 0A48 UCONIN 0A5E UCONT1 0B8D UCONTR 0B85 UCONV 0A67 UCOPCK 0AF6 UCOUT1 0A38 UCOUT2 0A3B UCRLF 0A05 UCSTS 0A53 UDBLC 0AD5 UDI0 0949 UDI1 0951 UDISP 0946 UERROR 0A24 UEX0 0A81 UEX1 0A84 UEX2 0A92 UEX3 0A9C UEXLF 0A00 UEXPR 0A7E UEXPR1 0A7C UEXPR3 0A71 UFI0 096A UFILL 095F UFILL0 0967 UGOTO 0974 UGOTO0 097C UHEXD 0ABB UHEXN 0AB3 UHILO 0AA9 UHILOX 0AA3 UHLSP 0A33 UIN 0B34 ULADR 0AC7 ULBYTE 0ACC UMEMSI 0ADB UMOVE 09A8 UMTEST 0984 UMV0 09B3 UMVO0 09B0 UNIBBL 0ADC UNIBOK 0AE6 UPCHK 0AF9 UPORT 0B22 UQ0 0B3D UQCHK 0AFC UQI1 0B3F UQI2 0B44 UQOUT 0B50 URETR1 0B7A URETRN 0B72 URTERR 0B87 USER 0003 USTAR0 0931 USTART 0922 USTORE 09BB USU0 09D6 USU1 09F2 USUBS 09C2 USUO0 09CC UT1 098F UT10 098C UT2 09A2 UTI 0B08 UVER0 0B60 UVERIF 0B58 UVERIO 0B63 WAIT 0A87 WAIT0 0A89 WAIT1 0A8C WAITC 0AC1 WAITD 0AEE WAITZ 0AB4 WFAULT 0002 WHAT 0812 WINDOW 0001 WLS0 0001 WLS1 0002 WRATSK 081E WRITE 0001 WRITSK 0885 WRTASK 081B No Fatal error(s) 0AF9 UPORT 0B22 UQ0 0B3D UQCHK 0AFC UQI1 0B3F UQI2 0B44 UQOUT 0B50 URETR1 0B7A URETRN 0B72 URTERR 0B87