MICRONIX SYSTEM CONFIGURATION MPZ80: Requires a Rev. 4.44 Prom. WIRE JUMPER - J1 to /PINT (Both in center near J2 to /NMI edge connector.) IC 16B - On solder side of board connect pin 13 to pin 14. LIFT PINS - IC 16B: Disconnect pins 13 & 14. IC 1D: Disconnect pin 8 Switch 16D: All ON except number 4 OFF - on RESET, permits booting off the floppy or mini-floppy when the letter B is entered on the system console. WUNDERBUSS I/O CONTROLLER (WB14): As primary I/O device. Boards not bearing a "Rev 2" sticker require the following modifications: (From here down to beginning of switch settings) These modifications can be made without removing the motherboard from the desktop enclosure. Instead, remove the six 8 X 32 phillips screws from the bottom closure panel to gain access to the solder side of the PC board. LIFT pin 2 of IC 4A. Solder an 8" wire jumper to this pin and feed it through the hole near pin 7 and connect it on the solder side of board to pin 8 of IC 13C. REMOVE wire jumper from 5A pin 5 where it connects to 5àpi an instal i instea betwee 5 pi an 4 pi 5. INSTALL a "Rev 2" sticker on component side of board. SWITCH 7C: Paddle 1: ON - generates a wait state on I/O and Interrupt Acknowledge cycles. Paddle 2: ON - Base address A7; not selected. Paddle 3: OF - Bas addres A6 normall selected with A3 to give a base address of 48h for the primary I/O device. Paddle 4: ON - Base address A5; normally not selected. Paddl5 ON - Base address A4; normally not selected. Paddle 6: OFF - Base address A3; normally selected. Paddle 7: OFF - Allows parallel handshake latch to respond to negative strobe. Paddle 8: OFF - Allows parallel handshake latch to respond to negative strobe. SWITCH 10A: Paddl 1 O - Wit paddle ON tell software to set baud rate at 9600. Paddle 2: ON - Baud rate. Paddle 3: ON - Baud rate. Paddles 4 through 8: Not dedicated - Don't care. JUMPER J1: NOT INSTALLED - Parallel port crosslatch. JUMPER J2: Jumpered A to B to permit WB I/O PIC to respond as master to Interrupt Acknowledge from the CPU. JUMPER J3: INSTALLED to enable the INTR/ output from the PIC to drive the S-100 PINT/ line. If not used as primary I/O device set Paddle 2 of Switch 7C OFF to prevent access by software. Jumper J2 B to C and remove J3. MULTI/O: As primary I/O device. Requires a Rev "MULTX-B" FPLA at 8A. LIFT pin 4 of IC 14C. JUMPER lifted pin to pin 2 of IC at location 13B. SWITCH 2D: Paddle 1: OFF to select A23 as extended address for on-board EPROM or RAM, putting it out of harm's way. Paddles 2 through 8: ON - Deselects A22 through A16 as extended addresses for on-board EPROM or RAM. SWITCH 7B: Paddle 1: ON -Enables PHANTOM from the S-100 onto the board. Paddle 2: ON - Base address A7 not selected. Paddle 3: OFF - Base address A6 selected. With A3 gives the desired base address of 48h. Paddle 4: ON - Base address A5 not selected. Paddle 5: ON - Base address A4 not selected. Paddle 6: OFF - Base address A3 selected. Paddle 7: OFF - Disables PWR/ from the S-100 to pin 21 of RAM/EPROM at 5D. Paddle 8: OFF - Disables PWR/ from the S-100 to pin 21 of RAM/EPROM at 6D. SWITCH 10B: Paddle 1: OFF - Causes MultI/O to ignore PHANTOM and enables extended addressing. Paddle 2: OFF - Causes on-board RAM/EPROM to come up bank de-selected on POJ or RESET. Paddles 3 and 4: OFF)- Select A15 and A14, de-select Paddles 5 and 6: ON ) A13 and A12 to address on-board RAM/EPROM at C000h. Paddl 7 OFƠ - De-select power-on-jum optio o thi board. Paddle 8: OFF - Selects R1 (6D) as the memory chip looked at for POJ instructions when that option employed. SLIDE JUMPER J4: B to C - Enables the PIC to gate an address vector onto the S-100 lines during an Interrupt Acknowledge cycle (INTA/). WIRE JUMPER J5 (lower-left corner): B to PINT/ - Enables interrupts onto the S-100 bus. SLIDE JUMPER J6: NOT INSTALLED: Keeps PHANTOM/ from the S-100 bus - not needed. FOR MULTI/O INSTALLED AS OTHER THAN PRIMARY I/O DEVICE: 1. Lift pin 16 of the PIC (location 10A). 2. Cut three traces at J5: Between C and VI/ 0. Between D and VI/ 1. Between E and VI/ 2. 3. Disconnect WIRE JUMPER J5 from PINT/ and re-install per table: MULTI/O NOT PRIMARY I/O DEVICE INSTALLED AS J5 SWITCH 7B I/O DEVICE JUMPER Paddles 3 (A6) 4 (A5) 5 (A4) SECOND B to VI/ 2 OFF ON OFF THIRD B to VI/ 3 OFF OFF ON FOURTH B TO VI/ 4 OFF OFF OFF HDCA HARD DISK CONTROLLER FOR THE M10, M20 OR M26: Install WIRE JUMPER from pads A and B (lower-left corner) to VI/ 0. On Rev. 3 boards only, cut trace leading to pin 10 of IC at 7A and install wire jumper from 7A pin 10 to 9A pin 9. DJDMA FLOPPY DISK CONTROLLER: Install WIRE JUMPER from J3 to VI/ 1 (lower left corner). Install SLIDE JUMPERS on J1 and J2 from B to C. Install SLIDE JUMPER on P3 between pins 2 & 3 to disable on-board serial I/O port. HDDMA HARD DISK CONTROLLER FOR THE M5: Install WIRE JUMPER from J5 to VI/ 0 (lower-left corner). MM65K STATIC RAM: Four boards required for 256K of consecutive memory commencing at 000000h. An LS2521 should be installed at 1D and not at 2D and the slide jumper at J3 should be removed to use extended addressing rather than bank select. CONSECUTIVE BOARDS Switch 1C: 1st 2nd 3rd 4th 5th 6th 7th 8th Paddle 1 (A16): ON OFF ON OFF ON OFF ON OFF Paddle 2 (A17): ON ON OFF OFF ON ON OFF OFF Paddle 3 (A18): ON ON ON ON OFF OFF OFF OFF Paddles 4 through 8 (A19 through A23 respectively): all ON Switch 5D: Block addressing - same on all boards Paddle 1 (A15): ON Block 0 - 0000H to 3FFFH Paddle 2 (A14): ON / Paddle 3 (A13): ON Block 1 - 4000H to 7FFFH Paddle 4 (A12): OFF / Paddle 5 (A11): OFF Block 2 - 8000H to BFFFH Paddle 6 (A10): ON / Paddle 7 (A9): OFF Block 3 - C000H to FFFFH Paddle 8 (A8): OFF 16 pin HEADER between 2D and 3D is used to disable 2K memory segments and should have NO slide jumpers installed. J1 and J2 should have slide jumpers installed to permit both the upper and lower 32K blocks to recognize PHANTOM/. J4 and J6 JUMPERED; J5 and J7 NOT JUMPERED, to ENABLE both the upper and lower 32K blocks of memory. DATA HEADERS in lower-right corner: DON'T CARE - select data bits when bank select is employed. SUMMARY MPZ80: Requires a Rev. 4.44 Prom; Switches all ON except number 4 OFF Wire jumper J1 to /PINT; J2 to /NMI Jumper IC 16B pin 13 to pin 14. Lift IC 16B pins 13 & 14 and IC 1D pin 8. WB14: Switch 7C: 1,2,4 & 5 ON; remainder OFF Switch 10A: 1,2 & 3 ON; remainder OFF J2 jumpered A to B; J3 Jumpered; J1 Not Jumpered Lift pin 2 of IC 4A and jumper it to pin 8 of IC 13C Jumper 5A pin 5 to 4A pin 5 instead of to 5C pin 2 Put a "Rev 2" sticker on component side of board. MULTIO: Switch 2D: 1 OFF; remainder ON Switch 7B: 3, 6, 7 & 8 OFF; remainder ON Switch 10B: 5 & 6 ON; remainder OFF Slide jumper J4 B to C Wire jumper installed from B to PINT/ (lower left) Slide jumper NOT installed at J6 HDC: Rev 3 boards require ECN #4 (Cut trace to 7A pin 10 and jumper 7A pin 10 to 9A pin 9. All boards require a wire jumper from A AND B to VI/ 0. DJDMA: Wire jumper installed from J3 to VI/ 1 (lower left) Slide jumpers on J1 and J2 from B to C Slide jumper installed on P3 from 2 to 3. HDDMA: Wire jumper installed from J5 to VI/ 0 (lower left) MM65K: Four boards required for 256K of consecutive memory commencing at 000000h. LS2521 installed at 1D. Slide jumper removed from J3. Switch 1C: From 1 to 8 represent A16 to A23 respectively. OFF selects that address line. Starting with all ON for the first board, count up one, in binary, for each additional board. Switch 5D: 1. 2. 3 and 6 ON, others OFF. Header between 2D & 3D: NO slide jumpers installed. J1 and J2: Jumpered. J4 and J6, Jumpered. J5 and J7 NOT jumpered. DATA HEADERS (lower-right corner): Not used - Don't care.