\ PROJECT UD3 \ FUNCTION WRITE PAL \ BY MICHAEL STOLOWITZ \ FILE WRITE.PAL \ DISK UD3 \ REVISION 4/28/83 \ 5/12/83 Inverted /MATCH \ 9/10/83 Reversed /EARLY & /LATE pins PALS 16R8 1. CLK 2. /CLK \ data/clock cell 3. QH \ msb of shift register 4. CMPR \ write ( if /read ) 5. PRECOMP \ enable write precomp 6. MFM \ MFM/FM 7. READ \ read/write 8. SEP-DATA \ read data 9. /MARK-BIT \ inh clk tran or read error 10. GND 11. OE 12. /EARLY \ write early or nominal 13. /LATE \ write late or nominal 14. /QI \ sr ext. 15. /QJ \ sr ext. 16. QA \ same as Qa of SR 17. MATCH \ compare = 18. GATE \ write gate 19. /QK \ sr ext. 20. VCC / QA = / /CLK * / SEP-DATA ( Load during data cell ) + /CLK * / QA ( Latch during clock cell ) / MATCH = READ * CMPR * / /MARK-BIT + READ * CMPR * / QA * QH + READ * CMPR * QA * / QH ( Set /MATCH on Qa <> Qh or MARK-BIT ) + READ * / MATCH ( Latch until / READ ) / /QI = / /CLK * QH ( In MFM or FM, Qi loads Qh in data cell ) + MFM * /CLK * / /QI ( In MFM, Qi latches during clock cell ) ( In FM, Qi clears during clock cell ) / /QJ = MFM * / /CLK * / /QI ( Qj follows Qi in data cell ) + MFM * /CLK * / /QJ ( In MFM, Qj latches during clock cell ) ( In FM, Qj is always zero ) / /QK = MFM * / /CLK * / /QJ ( Qk follows Qj during data cell ) + MFM * /CLK * / /QK ( In MFM, Qj latches during clock cell ) ( In FM, Qk is always zero ) / /EARLY = /CLK * /QK * /QJ * /QI * /MARK-BIT ( 0000 & 0001 ) + / /CLK * /QJ * / /QI * / QH ( 0010 & 1010 ) + / /CLK * /QJ * / /QI * QH * / PRECOMP ( 0011 & 1011 ) + / /CLK * / /QJ * / /QI ( 0110 & 0111 & 1110 & 1111 ) + /CLK * / /QK * /QJ * /QI * / QH * / PRECOMP ( 1000 ) Š + /CLK * / /QK * /QJ * /QI * QH * /MARK-BIT ( 1001 ) / /LATE = /CLK * /QK * /QJ * /QI * / QH * /MARK-BIT ( 0000 ) + /CLK * /QK * /QJ * /QI * QH * / PRECOMP ( 0001 ) + / /CLK * /QJ * / /QI ( 0010 & 0011 & 1010 & 1011 ) + / /CLK * / /QJ * / /QI * / QH * / PRECOMP ( 0110 & 1110 ) + / /CLK * / /QJ * / /QI * QH ( 0111 & 1111 ) + /CLK * / /QK * /QJ * /QI * /MARK-BIT ( 1000 & 1001 ) / GATE = / CMPR + READ PAL. TWEEK LIMIT 512 0 SAVE WR.DAT BYE 4/18/83 Changed /MATCH to latch until /READ. Addeä /MARK-BIÔ tï thå normaì clocë expressioîs foò EARLÙ anä LATE allowing the generation of mark bytes® .pa Š WRITE PAL Thå  WRITÅ PAÌ combineó thå functionó oæ FMF/FÍ encoder¬  writå precompensatioî  wheî writtinç anä seriaì bù biô comparisoî  useä for reading. Qi¬  Qê  anä Që forí á threå biô logicaì extentioî tï thå  datá shifô registeò whicè endó witè Qh®  Froí thió extention¬  anä thå CLOCK/DATÁ timinç signal¬  twï outputó arå decoded® Theså outputó contaiî  encodeä writå data®  Fouò stateó arå encodeä iî thå  twï signals®  Nï  transitioî ió requireä iî thå currenô celì iæ  botè signaló iî inactive® Á transitioî witè nominaì timinç ió requireä iæ  botè  signaló  arå active®  Aî earlù oò  latå  transitioî  ió required if the EARLY or LATE signal is asserted independently. MFÍ  encodinç requireó transitionó iî datá celló oæ NRÚ 1'ó anä iî clocë celló betweeî NRÚ 0's®  FÍ encodinç requireó transitionó iî ± datá celló anä alì clocë cells®  Tï perforí thå FÍ encoding¬ Qé  loadó  froí  Qè durinç datá celló  providinç  thå  datá  celì transitioî  froí  thå MFÍ rulå foò transitionó iî ±  datá  cells® Durinç clocë cells¬  Qé anä Qê arå botè cleared®  Thió forceó thå writtinç  oæ á transitioî iî thå clocë celì froí thå MFÍ encodinç rulå requirinç transitionó iî clocë celló btweeî 0 data cells. Thå  signaì  MARK-BIÔ  wilì inhibiô thå generatioî oæ  á  writå pulse®  Iô  ió  outpuô bù thå FPLÓ durinç thå biô celló  oæ  marë byteó  iî whicè clocë transitionó arå tï bå omitteä forcinç  thió PAÌ tï violatå its normal MFÍ encodinç rules. Wheî  REAÄ ió false¬  thå CMPR inpuô indicateó  WRITE-ENABLÅ and is reclock to provide WRITE-GATE. Thå  SEP-DATÁ signaì ió thå samå signaì thaô goeó tï thå  righô shifô  inpuô oæ thå datá shifô register®  Thió signaì ió  shifteä intï Qá oæ thå PAÌ wheneveò thå datá shifô registeò shifts®  Wheî CMPR ió asserteä iî conjunctioî witè READ¬ Qá ió compareä witè Qh® Iæ thå twï signaló arå unequal¬ /MATCÈ ió senä tï á restarô inpuô oæ thå 8085® Thuó thå hardwarå maù tesô á headeò bù loadinç thå referencå datá iî thå shifô registeò anä enablinç CMPR. Expressions for MFM encode and write precompensation: QK QJ QI QH C D | C D | C D | C D | WRITE | 0000 C C C NC 0001 C C D EC 0010 D ND Š0011 D D LD 0100 D C - 0101 D D - 0110 D D ED 0111 D D D ND 1000 D C C LC 1001 D C D NC 1010 D ND 1011 D D LD 1100 D C - 1101 D D - 1110 D D ED 1111 D D D ND Thå  termó  foò  thå EARLÙ outpuô includå alì oæ thå  earlù  oò normaì  transitionó  pluó thå latå transitionó  wheî  precomð  ió inactive® Similarly¬ thå termó foò LATÅ includå alì oæ thå normaì oò  latå  transitionó  pluó thå earlù transitionó iæ  precomð  ió inactive® Minimizatioî waó requireä tï reducå thå totaì numbeò oæ terms to the eight available within the PAL. 5/12/83 Inverted /MATCH output for low on not equal. 9/10/83 Reversed pin numbers on /EARLY and /LATE to match board layout