GROUP2	EQU	2	;CODE FOR SECOND ACE (J2)
BASE	EQU	48H	;BASE I/O ADDRESS SET BY SW-8C
BASE2	EQU	10H	;BASE I/O ADDRESS FOR BD 2
GRPCTL	EQU	BASE+7	;BOARD GROUP CONTROL PORT
DLL	EQU	BASE	;ACE BAUD RATE DIVISOR (LSB)
DLM	EQU	BASE+1	;ACE BAUD RATE DIVISOR (MSB)
IER	EQU	BASE +1	;ACE INTERRUPT ENABLE REGISTER
LCR	EQU	BASE +3	;ACE LINE CONTROL REGISTER
LSR	EQU	BASE +5	;ACE LINE STATUS REGISTER
RBR	EQU	BASE	;ACE RECEIVER BUFFER REGISTER
THR	EQU	BASE	;ACE TRANSMITTER HOLDING REGISTER
DLAB	EQU	80H	;DIVISOR LATCH ACCESS BIT
THRE	EQU	20H	;LINE STATUS REGISTER THRE BIT
DR	EQU	1	;LINE STATUS REGISTER DR BIT
BAUDL	EQU	12	;DIVISOR LATCH LOW BYTE - - 9600 BAUD
BAUDH	EQU	0	;DIVISOR LATCH HIGH BYTE - - 9600 BAUD
WLS0	EQU	1	;WORD LENGTH SELECT BIT 0 - 8 BIT WORD
WLS1	EQU	2	;WORD LENGTH SELECT BIT 1 - 8 BIT WORD
STB	EQU	4	;STOP BIT COUNT - 2 STOP BITS
IMASK	EQU	0	;INTERRUPT MASK - DISABLE ALL
;
GRPCTL2	EQU	BASE2+7	;BOARD GROUP CONTROL PORT
DLL2	EQU	BASE2	;ACE BAUD RATE DIVISOR (LSB)
DLM2	EQU	BASE2+1	;ACE BAUD RATE DIVISOR (MSB)
IER2	EQU	BASE2+1	;ACE INTERRUPT ENABLE REGISTER
LCR2	EQU	BASE2+3	;ACE LINE CONTROL REGISTER
LSR2	EQU	BASE2+5	;ACE LINE STATUS REGISTER
RBR2	EQU	BASE2	;ACE RECEIVER BUFFER REGISTER
THR2	EQU	BASE2	;ACE TRANSMITTER HOLDING REGISTER
;
	ORG	100H
INIT	MVI	A,GROUP2
	OUT 	GRPCTL	;SELECT SECOND SERIAL DEVICE
	OUT	GRPCTL2
	MVI	A,DLAB+WLS0+WLS1+STB
	OUT	LCR
	OUT	LCR2
	MVI	A,BAUDL
	OUT	DLL
	OUT	DLL2
	MVI	A,BAUDH
	OUT	DLM
	OUT	DLM2
	MVI	A,WLS0+WLS1+STB
	OUT	LCR
	OUT	LCR2
	XRA	A
	OUT	LSR
	OUT	LSR2
	MVI	A,IMASK
	OUT	IER
	OUT	IER2
;
OUTONE	MVI	C,'C'
CONOUTL IN	LSR
	ANI	THRE
	JZ	CONOUTL
	MOV	A,C
	OUT	THR
CONIN	IN	LSR2
	ANI	DR
	JZ	CONIN
	IN	RBR2
CKINT	LDA	0E3F9H
	ANI	4
	JNZ	OUTONE
	JMP	0