TITLE		-=< MULTI I/O TEST >=-

		* REVISED - 3/15/81

*		EQUATES			*

MASBASE	EQU	10H	;BASE OF MASTER MULTI I/O BOARD.
TSTBASE EQU	0	;BASE OF MULTI I/O UNDER TEST.
GRP	EQU	7	;GROUP SELECTION PORT.

GROUP0	EQU	0	;WHEN SENT TO BASE+GRP, 1 OF THE 4
GROUP1	EQU	1	;GROUPS OF 7 I/O PORTS IS SWITCHED INTO
GROUP2	EQU	2	;THE I/O SPACE. 0=PAR, CLK, PIC, BANKS.
GROUP3	EQU	3	;1=SERIAL1 - 2=SERIAL2 - 3=SERIAL3.

* ALLOCATION OF PORTS TO GROUPS *
PARPORT	EQU	GROUP0	;2 1/8 PARALLEL OUTPUTS AND 1 INPUT.
CLOCK	EQU	GROUP0	;REAL TIME CLOCK AND INTERRUPT TIMER.
PIC	EQU	GROUP0	;PROGRAMMABLE INTERRUPT CONTROLLER.
BANKS	EQU	GROUP0	;BANK SELECTION PORT.

SERPRT1	EQU	GROUP1	;SERIAL PORT #1, ACE @ 4A, INT. LEVEL 3.
SERPRT2	EQU	GROUP2	;SERIAL PORT #2, ACE @ 3A, INT. LEVEL 4.
SERPRT3	EQU	GROUP3	;SERIAL PORT #3, ACE @ 5A, INT. LEVEL 5.

* GROUP 0 PORT DEFINITION *
PARIO0	EQU	0	;PARALLEL OUTPUT LATCH #0 - PARALLEL INPUT PORT.
PAROUT1	EQU	1	;PARALLEL OUTPUT LATCH #1.
CLOCKIO	EQU	2	;CLOCK AND TIMER SET AND READ PORT.
PAROUT2	EQU	2	;RIBBON LIFT OUTPUT (1/8 PORT).
BANK	EQU	2	;BANK SELECT PORT.
CLKINTC	EQU	3	;INTERRUPT TIMER RESET PORT.
PIC0	EQU	4	;INTERRUPT INITIALIZATION AND CONTROL WORD #0.
PIC1	EQU	5	;INTERRUPT INITIALIZATION AND CONTROL WORD #1.

* GROUPS 1, 2, 3 PORT DEFINITION *
RBR	EQU	0	;RECEIVER BUFFER REGISTER.
THR	EQU	0	;TRANSMITTER HOLDING REGISTER.
IER	EQU	1	;INTERRUPT ENABLE REGISTER.
DLL	EQU	0	;BAUD RATE DIVISOR LATCH (LEAST SIGNIFICANT).
DLM	EQU	1	;BAUD RATE DIVISOR LATCH (MOST SIGNIFICANT).
IIR	EQU	2	;INTERRUPT IDENTIFICATION REGISTER.
LCR	EQU	3	;LINE CONTROL REGISTER.
MCR	EQU	4	;MODEM CONTROL REGISTER.
LSR	EQU	5	;LINE STATUS REGISTER.
MSR	EQU	6	;MODEM STATUS REGISTER.

*		MEMORY ADDRESS DEFINITIONS		*

BDOS	EQU	0005	;SYSTEM CALL ENTRY POINT.
WBOOT	EQU	0000	;WARM START ENTRY.
TPA	EQU	0100H	;TRANSIENT PROGRAM AREA.

*		DATA WORD DEFINITIONS			*

ZERO	EQU	0000

*		DATA BYTE DEFINITIONS			*

IMASK	EQU	0	;INTERRUPT MASK BYTE.
BAUD0	EQU	12	;LEAST SIGNIFICANT BAUD RATE DIVISOR.
BAUD1	EQU	0	;MOST SIGNIFICANT BAUD RATE DIVISOR.
CR	EQU	0DH	;CARRIAGE RETURN.
LF	EQU	0AH	;LINE FEED.
PERIOD	EQU	2EH	;[.]
DASH	EQU	2DH	;[-]
EQLS	EQU	3DH	;[=]
SPACE	EQU	20H	;[ ]
BELL	EQU	7	;[^G]
ESC	EQU	1BH	;ESCAPE.

*		BIT DEFINITIONS			*

* [IER] INTERRUPT ENABLE REGISTER. *
EDRI	EQU	1	;ENABLE DATA READY INTERRUPT.
ETHREI	EQU	2	;ENABLE TXMTR HOLDING REGISTER EMPTY INTERRUPT.
EDCDI	EQU	4	;ENABLE DATA CARRIER DETECT INTERRUPT.
EMSI	EQU	8	;ENABLE MODEM STATUS INTERRUPT.

* [IIR] INTERRUPT IDENTIFICATION REGISTER. *
INTPEND	EQU	1	;INTERRUPT PENDING (ACTIVE LOW).
IID0	EQU	2	;INTERRUPT IDENTIFICATION BIT 0.
IID1	EQU	4	;INTERRUPT IDENTIFICATION BIT 1.

* [LCR] LINE CONTROL REGISTER OF SERIAL DATA TRANSMISSION PROTOCOL. *
WLS0	EQU	1	;WORD LENGTH SELECT BIT 0.
WLS1	EQU	2	;WORD LENGTH SELECT BIT 1.
STB	EQU	4	;STOP BIT SELECT.
PEN	EQU	8	;PARITY ENABLE.
EPS	EQU	10H	;EVEN PARITY SELECT.
SPAR	EQU	20H	;STICK PARITY.
SBRK	EQU	40H	;SET BREAK.
DLAB	EQU	80H	;BAUD RATE DIVISOR LATCH ACCESS BIT.

* [MCR] MODEM CONTROL REGISTER OF EIA LINE DRIVERS. *
DTR	EQU	1	;DATA TERMINAL READY.
RTS	EQU	2	;REQUEST TO SEND.
OUT1	EQU	4	;USER DEFINED OUTPUT (IF LOOP, OUT1 = RI)
OUT2	EQU	8	;USER DEFINED OUTPUT (IF LOOP, OUT2 = DCD)
LOOP	EQU	10H	;ACE DIAGNOSTIC. SETS ALL COMMUNICATION TO HALF DUPLEX.

* [LSR] LINE STATUS REGISTER OF SERIAL DATA RECEPTION. *
DR	EQU	1	;DATA READY.
OE	EQU	2	;OVERRUN ERROR.
PE	EQU	4	;PARITY ERROR.
FE	EQU	8	;FRAMING ERROR.
BI	EQU	10H	;BREAK INTERRUPT.
THRE	EQU	20H	;TRANSMITTER HOLDING REGISTER EMPTY.
TSRE	EQU	40H	;TRANSMITTER SHIFT REGISTER EMPTY.

* [MSR] MODEM STATUS REGISTER OF EIA LINE RECEIVERS. *
DCTS	EQU	1	;DELTA CLEAR TO SEND.
DDSR	EQU	2	;DELTA DATA SET READY.
TERI	EQU	4	;TRAILING EDGE RING INDICATOR.
DDCD	EQU	8	;DELTA DATA CARRIER DETECT.
CTS	EQU	10H	;CLEAR TO SEND.
DSR	EQU	20H	;DATA SET READY.
RI	EQU	40H	;RING INDICATOR.
DCD	EQU	80H	;DATA CARRIER DETECT.

*	END OF EQUATES	-	BEGINNING OF CODE.	*

	ORG	TPA	;ORIGINATE CODE AT THE TRANSIENT PROGRAM AREA.

*		FIRST LEVEL ROUTINES		*

ENTRY:	DW	ZERO	;HOT PATCH AREA FOR JMP, CALL, RST, OR INT.
	DW	ZERO	;THESE FOUR BYTES USED FOR PROGRAM DEVELOPMENT ONLY.

* INITIALIZATION *
MAIN:	LXI SP,STACK	;SET UP 32 LEVEL STACK AT END OF THIS CODE.
	LXI D,MSG	;INITIAL SIGN-ON, SEEN ONLY ONCE,
	CALL PMSG	;SENT TO CONSOLE.
	CALL CLRBRD0	;INITIALIZE THE MASTER MULTI I/O.
	CALL CLRBRD1	;INITIALIZE THE MULTI I/O UNDER TEST.

* COMMAND DELEGATION *
MLOOP:	CALL GETKEY	;WAIT FOR A COMMAND.  RETURN W/CHAR. IN 'A'.
	ORA A
	JZ MLOOP
	CPI '0'
	JZ WBOOT	;EXIT TO CP/M.
	CPI '1'
	CZ SERTST1	;TEST SERIAL PORT #1.
	CPI '2'
	CZ SERTST2	;TEST SERIAL PORT #2.
	CPI '3'
	CZ SERTST3	;TEST SERIAL PORT #3.
	CPI '4'
	CZ PARTST	;TEST THE PARALLEL PORTS.
	CPI '5'
	CZ NOTIMP	;TEST THE INTERRUPT STRUCTURE.
	CPI '6'
  	CZ NOTIMP	;TEST THE CLOCK AND INT. TIMER.
	CPI '7'
	CZ NOTIMP	;TEST THE RAM AND EPROM.
	CPI ESC
	JZ MAIN		;RE-INITIALIZE.
	LXI D,MSG0	
	CALL PMSG	;PROMPT NEXT COMMAND.

	JMP MLOOP	;GET NEXT COMMAND.

SERTST1:LXI D,MSG1	
	CALL PMSG	;PRINT SERIAL TEST MESSAGE,
	MVI E,'1'	;AND THE PORT#.
	MVI C,2
	CALL BDOS
	MVI A,SERPRT1	;PASS THE PORT# TO THE TEST.
	JMP SERTEST

SERTST2:LXI D,MSG1
	CALL PMSG	;PRINT SERIAL TEST MESSAGE,
	MVI E,'2'	;AND THE PORT #.
	MVI C,2
	CALL BDOS
	MVI A,SERPRT2	;PASS THE PORT# TO THE TEST.
	JMP SERTEST

SERTST3:LXI D,MSG1
	CALL PMSG	;PRINT SERIAL TEST MESSAGE,
	MVI E,'3'	;AND THE PORT #.
	MVI C,2
	CALL BDOS
	MVI A,SERPRT3	;PASS THE PORT# TO THE TEST.
	JMP SERTEST

* PARALLEL PORT TESTS *
PARTST:	LXI D,MSG4
	CALL PMSG	;PRINT THE PARALLEL TEST MESSAGE.
	MVI A,PARPORT
	OUT MASBASE+GRP	;SET ACCESS TO THE MASTER'S PARALLEL PORTS.
	OUT TSTBASE+GRP	;SET ACCESS TO THE TEST BOARD'S PARALLEL PORTS.
	XRA A
	OUT MASBASE+PAROUT1	;CHANNEL TEST PAROUT0 TO MAST PARIN VIA JIG.
	PUSH PSW		;FLAG THE JIG'S SWITCH FOR LATER EXAMINATION.
	JMP PARTST1

*		SECOND LEVEL ROUTINES		*

CLRBRD0:MVI A,SERPRT1
	STA CLRPRT0
	CALL MASINIT	;CLEAR MASTER SERIAL #1.
	MVI A,SERPRT2
	STA CLRPRT0
	CALL MASINIT	;CLEAR MASTER SERIAL #2.
	MVI A,SERPRT3
	STA CLRPRT0
	CALL MASINIT	;CLEAR MASTER SERIAL #3.
	RET

CLRBRD1:MVI A,SERPRT1
	STA CLRPRT1
	CALL TSTINIT	;CLEAR TEST SERIAL #1.
	MVI A,SERPRT2
	STA CLRPRT1
	CALL TSTINIT	;CLEAR TEST SERIAL #2.
	MVI A,SERPRT3
	STA CLRPRT1
	CALL TSTINIT	;CLEAR TEST SERIAL #3.
	RET

SERTEST:STA MSTPRT	;THIS IS THE SERIAL TEST ROUTINE FOR ALL THREE PORTS.
	STA MINPRT	;ON ENTRY, 'A' CONTAINS THE PORT # TO BE TESTED.
	STA MRDYPRT	;THE STATUS, INPUT AND OUTPUT ROUTINES ARE SET TO
	STA MOUTPRT	;ACCESS THE APPROPRIATE PORT BY THESE EIGHT 'STORE A'S.
	STA TSPORT	;THIS METHOD OF MODIFYING THE ROUTINES THEMSELVES IS
	STA TINPRT	;ALSO USED IN THE INITIALIZATION PROCESS.
	STA TRDYPRT	;THE BYTES THAT THESE 8 ADDRESSES POINT TO ARE
	STA TOUTPRT	;INITIALLY 0, AND MUST BE SET BEFORE THEY ARE USED.
	MVI B,0			;CLEAR BYTE TO BE SENT, RECEIVED AND COMPARED.
SLOOP:	INR B		;SET NEXT ITERATION.
	MOV C,B		;THE OUTPUT ROUTINE SENDS REGISTER 'C'
	CALL MOUT		;THROUGH THE JIG AND INTO THE TEST BOARD,
 	CALL TIN		;TO BE RECEIVED IN 'A' AND PASSED 
	MOV C,A				;TO THE TEST BOARD'S OUTPUT ROUTINE,
	CALL TOUT		;TO BE SENT THROUGH THE JIG INTO THE MASTER
	CALL MIN		;WHICH IS RECEIVED IN 'A' AND COMPARED
	CMP B		;WITH WHAT WAS SENT ORIGINALLY.
	JNZ ERR1				;FLAG ERROR IF NO MATCH FOUND.
	CPI 0			;CHECK FOR 256 BYTES SENT AND RECEIVED.
	JNZ SLOOP	;SEND THE NEXT IF NOT.
	MVI E,PERIOD
	MVI C,2
	CALL BDOS	;PRINT A DOT FOR EVERY 256 BYTES TESTED GOOD.
	CALL GETKEY
	ORA A			;CHECK FOR KEYDOWN.
	JZ SLOOP	;CONTINUE IF NOT.
	CPI ESC
	JZ MAIN		;ESCAPE.
	CPI SPACE
	CZ PAUSE	;PAUSE.
	JMP SLOOP		;IGNORE ALL OTHER KEYS.

PARTST1:INR A
	MOV B,A
	OUT MASBASE+PARIO0
	IN TSTBASE+PARIO0
	CMA
	MOV C,A
	POP PSW
	PUSH PSW
	JZ LATCH0
	MOV A,C
	OUT TSTBASE+PAROUT1
	JMP SWAP
LATCH0:	MOV A,C
	OUT TSTBASE+PARIO0
SWAP:	IN MASBASE+PARIO0
	CMA
	CMP B
	JNZ ERR2
	CPI 0
	JNZ PARTST1
	POP PSW
	JNZ PASS
	MVI A,8
	ORA A
	PUSH PSW
	OUT MASBASE+PAROUT1
	MVI E,EQLS
	JMP PASSED
PASS:	XRA A
	PUSH PSW
	OUT MASBASE+PAROUT1
	MVI E,DASH
PASSED:	MVI C,2
	CALL BDOS
	CALL GETKEY
	ORA A
	JZ PARTST1
	CPI ESC
	JZ MAIN
	CPI SPACE
	CZ PAUSE
	JMP PARTST1

*		THIRD LEVEL ROUTINES		*

* INITIALIZATION *
MASINIT:
CLRPRT0	EQU	$+1
	MVI A,ZERO
	OUT MASBASE+GRP
	MVI A,DLAB
	OUT MASBASE+LCR
	MVI A,BAUD0
	OUT MASBASE+DLL
	MVI A,BAUD1
	OUT MASBASE+DLM
	MVI A,WLS0+WLS1+STB
	OUT MASBASE+LCR
	MVI A,IMASK
	OUT MASBASE+IER
	RET

TSTINIT:
CLRPRT1	EQU	$+1
	MVI A,ZERO
	OUT TSTBASE+GRP
	MVI A,DLAB
	OUT TSTBASE+LCR
	MVI A,BAUD0
	OUT TSTBASE+DLL
	MVI A,BAUD1
	OUT TSTBASE+DLM
	MVI A,WLS0+WLS1+STB
	OUT TSTBASE+LCR
	MVI A,IMASK
	OUT TSTBASE+IER
	RET

* STATUS ROUTINES *
MSTAT:
MSTPRT	EQU	$+1
	MVI A,ZERO
	OUT MASBASE+GRP
	IN MASBASE+LSR
	ANI DR
	MVI A,0
	RZ
	CMA
	RET

MRDY:
MRDYPRT	EQU	$+1
	MVI A,ZERO
	OUT MASBASE+GRP
	IN MASBASE+LSR
	ANI THRE
	MVI A,0
	RZ
	CMA
	RET

TSTAT:
TSPORT	EQU	$+1
	MVI A,ZERO
	OUT TSTBASE+GRP
	IN TSTBASE+LSR
	ANI DR
	MVI A,0
	RZ
	CMA
	RET

TRDY:
TRDYPRT	EQU	$+1
	MVI A,ZERO
	OUT TSTBASE+GRP
	IN TSTBASE+LSR
	ANI THRE
	MVI A,0
	RZ
	CMA
	RET

* INPUT ROUTINES *

MIN:
MINPRT	EQU	$+1
	MVI A,ZERO
	OUT MASBASE+GRP
MINP1:	CALL MSTAT
	ORA A
	JZ MINP1
	IN MASBASE+RBR
	RET


TIN:
TINPRT	EQU	$+1
	MVI A,ZERO
	OUT TSTBASE+GRP
TINP1:	CALL TSTAT
	ORA A
	JZ TINP1
	IN TSTBASE+RBR
	RET

* OUTPUT ROUTINES *
MOUT:
MOUTPRT	EQU	$+1
	MVI A,ZERO
	OUT MASBASE+GRP
	CALL MRDY
	ORA A
	JZ MOUT
	MOV A,C
	OUT MASBASE+THR
	RET

TOUT:
TOUTPRT	EQU	$+1
	MVI A,ZERO
	OUT TSTBASE+GRP
	IN TSTBASE+LSR
	CALL TRDY
	ORA A
	JZ TOUT
	MOV A,C
	OUT TSTBASE+THR
	RET

* ERROR ROUTINES *
ERR1:	LXI D,MSG9
	CALL PMSG
	LDA MSTPRT
	ADI 30H
	MOV E,A
	MVI C,2
	CALL BDOS
	STC
	RET

ERR2:	LXI D,MSG10
	CALL PMSG
	JMP MLOOP

* UTILITY SUBROUTINES *
PAUSE:	LXI D,MSG8
	CALL PMSG
WAIT:	CALL GETKEY
	CPI SPACE
	JNZ WAIT
	RET

GETKEY:	MVI C,11
	CALL BDOS
	ORA A
	RZ
	MVI C,1
	CALL BDOS
	RET

NOTIMP:	LXI D,MSG5

PMSG:	MVI C,9
	CALL BDOS
	RET

*			MESSAGES			*

MSG:	DB CR,LF
	DB '		-=< MULTI I/O DIAGNOSTICS >=-',CR,LF
	DB CR,LF
	DB '	REVISED 3/10/81 - (C) D.M.G. - MORROW DESIGNS',CR,LF
	DB CR,LF
	DB 'SELECT TEST BY NUMBER -',CR,LF
	DB '0, TO EXIT TO CP/M.',CR,LF
	DB '1, SERIAL PORT ONE (1).',CR,LF
	DB '2, SERIAL PORT TWO (2).',CR,LF
	DB '3, SERIAL PORT THREE (3).',CR,LF
	DB '4, PARALLEL PORT TESTS.',CR,LF
	DB '5, INTERRUPT REQUEST TEST.',CR,LF
	DB '6, INTERRUPT TIMER & CLOCK TEST.',CR,LF
	DB '7, RAM/EPROM TESTS.'
MSG0:	DB CR,LF,'=>',24H
MSG1:	DB CR,LF,'NOW TESTING SERIAL PORT #',0,24H
MSG2:	DB '#2',0,24H
MSG3:	DB '#3',0,24H
MSG4:	DB CR,LF,'PARALLEL PORT TESTS.',24H
MSG5:	DB CR,LF,'UNDEFINED.',CR,LF,24H
MSG6:	DB CR,LF,'#6',CR,LF,24H
MSG7:	DB CR,LF,'#7',CR,LF,24H
MSG8:	DB CR,LF,BELL,'HIT SPACE BAR.',CR,LF,24H
MSG9:	DB CR,LF,BELL,'ERROR AT SERIAL PORT #',24H
MSG10:	DB CR,LF,BELL,'ERROR AT PARALLEL PORT #',24H
CRLF:	DB CR,LF,24H

LENGTH	EQU	$
STACK	EQU	LENGTH+64	;32 LEVELS.

	END