SBTTL 'Initialization Section (28_Dec_84)'
	PAGE
;======================================================================
;
;	Copyright 1984
;	Morrow Designs, Inc.
;	San Leandro, Ca.
;
;
; Module Description:
;--------------------
;	This file includes all of the code that is unique to initialization.
;
;----------------------------------------------------------------------
; Index (13_Nov_84)
;------------------
;
;	INITC	Cold Start Initialization (Reset)
;	INITW	Warm Start Initialization (Reset & After dip switches changed)
;
;	SLFTST	Self Test Routine
;	KTEST	Keyboard Test
;	MTEST	Memory Test
;
;	INIUART	Initialize the Uart Main Line
;	SETBAUD	Determine the Baud Rate
;	SETUART	Set the Uart's Baud Rate
;	INIT8	Set the Uart's Reciever/Transmitter Format
;
;	GETSW	Get the value of the Dip Switches
;	INITBUF	Initialize the Input Buffers
	PAGE

;----------------------------------------------------------------------
; Cold Start Initialization (28_Dec_84)
;--------------------------------------
;	1) Normal Reset Entry
;
INITC:	LDA	#0		;disable NMI handling
	STA	BAUD		;put kbrd in quiescent state
	STA	BDREG
	CLD
	TAX			;X:= 0
CLDLP0:	STA	RAM,X		;Repeat	Page_Zero,x:= 0
	INX			;	Increment the Index
	BNE	CLDLP0		;Until (All of Page Zero is Cleared)

	LDX	#7		;X:= Length of Page Zero NMI Vector Routines
CLDLP1:	LDA	NMISTR,X	;Repeat
	STA	VCTNMI,X	;	Install Next Byte of Vector
	DEX			;	Decrement Index/Counter
	BPL	CLDLP1		;Until (Counter lt 0)

	LDX	#16		;clear bit 6 of status reg on 6545
	STX	CRTC
	LDA	CRTC+1		;by reading LPEN register
	LDA	CRTC		;read CRTC status register
	AND	#%01000000
	CMP	#%00000000	;see if 6545
	BNE	CLDSK1		;if not 6545, then init as 6845

	LDX	#15		;init CRTC (6545)
CLDLP2:	STX	CRTC
	LDA	SETUP65,X
	STA	CRTC+1
	DEX
	BPL	CLDLP2
	JMP	CLDSK2
CLDSK1:	LDX	#15		;init CRTC (6845)
CLDLP3:	STX	CRTC
	LDA	SETUP68,X
	STA	CRTC+1
	DEX
	BPL	CLDLP3

CLDSK2:	LDA	#' '		;set to clear screen to spaces
	STA	CLRCHAR
	JSR	CLRSCR		;clear screen
	JSR	SLFTST		;test for KBRD, and test RAM
	RTS			;Return
	PAGE

;----------------------------------------------------------------------
; Warm Start Initialization (28_Dec_84)
;--------------------------------------
;	1) re-initialization after DIP Switch change starts here
;
INITW:	JSR	GETSW		;get dip switch setting
	JSR	INIUART		;init BAUD port and USART
	JSR	INITBUF		;fill in and out buffers with 0ffh
	LDA	#0		;set function key sequence type
	LDY	DIP1		;depends on switch 8 of dip switch
	BMI	WRMSK1		;if 1, then morrow function sequence

	LDA	#$FF		;else, set for Televideo lead in
WRMSK1:	STA	FNCNTYP		;set function type
	LDA	#0		;clear ESCRCVD flag (used in monitor mode)
	STA	ESCRCVD

	LDA	ATTTAB+0
	STA	ATTRIB		;Set Normal Video Mode
	LDA	#' '		;set to clear to spaces
	STA	CLRCHAR
	JSR	CLRSCR		;clear the screen
	LDA	#2		;set default attribute for BRIGHT/DIM
	STA	DEFINV

	LDA	#0		;set default cursor to Block
	STA	DCURTYP
	JSR	CURST2		;set cursor type to what's in A reg

	CLI
	LDA	#CAPSOFF	;turn off caps lock light
	JSR	PUTKEY
	LDA	#AUTON		;turn on auto repeat
	JSR	PUTKEY
	LDA	#OFLNOFF	;turn off OFF LINE LED
	JSR	PUTKEY
	LDA	#BEEP		;BEEP!!
	JSR	PUTKEY
	RTS			;Return
	PAGE

;----------------------------------------------------------------------
; Self-Test Routine (14_Dec_84)
;------------------------------
;
SLFTST:	JSR	KTEST		;Test the Keyboard
	JSR	MTEST		;Test Ram Memory
	RTS

;----------------------------------------------------------------------
; Test the Keyboard
;------------------
;
KTEST:	LDX	BAUD		;While (Keyboard is trying to send)
	BPL	KTSK1

	JSR	GETKEY		;	get the key from keyboard
	JMP	KTEST

KTSK1:	LDA	#$1		;assert attention to KBRD
	ORA	BDREG
	STA	BAUD
	LDX	#200		;Time_Delay:= 4 ms ( 200 * 20 Micro secs )

KTLP1:	TXA			;Repeat
	PHA			;	(save Time_Delay)
	LDX	2
	JSR	KDLY		;	wait 20 micro seconds
	LDX	BAUD		;	If (Ack Recieved from Keyboard)
	BMI	KTSK2		;		Goto Keyboard Ok

	PLA			;	decrement time out count
	TAX
	DEX
	BNE	KTLP1		;Until (Time_Delay eq 0)

	LDA	KMESG		;point to memory fail message
	STA	MESG
	LDA	KMESG+1
	STA	MESG+1
	JSR	PRNTMSG		;print message 
	PLA
	PLA			;(preserve stack)
	JMP	SLFTST		;wait for the keyboard to be connected

KTSK2:	PLA			;fix stack
	LDA	#BEEP		;now, we have to give this ack a character
	SEI			;and set up the needed parameters
        PHA
	LDY	#8
	JMP	ACK1		;go send it a key, and return to Selftest
	PAGE

;----------------------------------------------------------------------
; Test Memory
;------------
;
MTEST:	LDY	#0

MTLP1:	TYA
	STA	CRAM,Y
	STA	CRAM+1021,Y
	STA	ARAM,Y
	STA	ARAM+509,Y
	INY
	BNE	MTLP1

MTLP2:	TYA
	CMP	CRAM,Y
	BNE	MTSK1

	CMP	CRAM+1021,Y
	BNE	MTSK1

	CMP	ARAM+509,Y
	BNE	MTSK1

	CMP	ARAM,Y
	BNE	MTSK1

	INY
	BNE	MTLP2
	RTS

MTSK1:	LDA	#BEEP		;beep the bell 
	JSR	PUTKEY

	LDA	MMESG		;point to memory fail message
	STA	MESG
	LDA	MMESG+1
	STA	MESG+1
	JSR	PRNTMSG		;print message

SELF:	JMP	SELF		;and loop forever
	PAGE
	
;----------------------------------------------------------------------
; Uart Initialization
;--------------------
;
INIUART:JSR	SETBAUD		;determine baud rate selection bits
	JSR	SETUART		;setup UART for proper BAUD rate, etc
	JSR	INIT8		;set status of bit 8 parity, or mark, or space
	RTS

;----------------------------------------------------------------------
; Determine the Baud Rate Settings
;---------------------------------
;
SETBAUD:LDA	BDREG		;get current contents of baud register
	AND	#$F9		;Clear BD0 and BD1
	STA	BDREG
	LDA	DIP1		;get dipsw value
	AND	#$03		;get baud rate selection bits
	ASL	A		;align with BDREG
	ORA	BDREG		;set/clr baud bits
	STA	BDREG		;Save it
	STA	BAUD		;and set baud bits
	RTS
	PAGE

;----------------------------------------------------------------------
; Set the Uart Baud Rate
;-----------------------
;
SETUART:LDX	#$80		;after setting baud rate, wait to settle
SULP1:	DEX
	BNE	SULP1

	LDA	#$80		;reset USART
	STA	S1STAT
	TAX
	TAX			;WAIT
	STA	S1STAT
	LDA	#$40
	STA	S1STAT		;Put USART in command mode
	LDA	DIP1		;get dip switch settings
	AND	#%00001100	;get the parity select bits
	ASL	A
	ASL	A		;align them for USART Mode byte
	STA	TEMP		;put it aside
	LDA	DIP1		;get dip switch 
	AND	#%00000010	;determine if it needs /16 or /64
	LSR	A		;move the determining bit over
	ORA	TEMP		;get parity select bits back
	ORA	#%01001110	;OR in USART MODE boiler plate (8-data, 1-stop)
	STA	S1STAT		;set USART Mode
	LDA	#%00110111	;get enable byte for USART
	STA	S1STAT		;Enable USART
	STA	UARTCMD		;save it in command instr. register
	LDA	S1DATA		;Flush one character
	RTS

;----------------------------------------------------------------------
; Set Transmission/Reception Format
;----------------------------------
;
INIT8:	LDA	DIP1		;get dip setings
	LSR	A		;get parity on/off status
	LSR	A
	TAX
	AND	#%00000001
	STA	PARSTAT		;save it in parity status
	TXA
	LSR	A
	AND	#%00000001	;get whether mark or space/ odd/even
	STA	BIT8
	RTS
	PAGE

;----------------------------------------------------------------------
; Read the Dip Switches
;----------------------
;
GETSW:	LDA	DIPSW11		; READ DIP SWITCH
	ASL	A
	STA	DIP1
	LDA	DIPSW12		; GET 8TH SWITCH
	AND	#01		; MASK OFF BAD BITS
	ORA	DIP1		; ASSEMBLE THE 8 DATA BITS
	STA	DIP1		; save the dipsw settings
	RTS

;----------------------------------------------------------------------
; Initialize the Input Buffers (17_Dec_84)
;-----------------------------------------
;	1) This routine initializes the buffer block to zero and then sets
;	   up the Input Buffer Pointers and Counter.
;	2) Notice that the key buffer is also set to nulls.
;
INITBUF:LDA	#0		;A:= 0
	LDY	#42		;Index/Counter:= Top of Buffer_Pointer Block

ITBLP0:	STA	INCNT-1,Y	;Repeat	Set the Buffer_Pointer to Zero
	DEY			;	Decrement the Index/Counter
	BNE	ITBLP0		;Until (the whole pointer block has been 0'ed)

	LDA	#HIGH INBUF	;Initialize the pointers for input buffer
	STA	INEP+1
	STA	INSP+1
	LDA	#(HIGH INLEN)
	STA	INCNT+1
	RTS			;Return

	END