;    I/O Port addresses for Z80 chip set
;    based system with wd1797 FDC

	; chip bases

p$zdma		equ 0
p$wd1797	equ 4
p$zpio1		equ 8
p$zctc1		equ 12
p$zpio2		equ 16
p$boot		equ 20	; OUT disables boot EPROM
p$zdart		equ 28	; console 1 and printer 1
p$zpio3		equ 36
p$zsio1		equ 40
p$zsio2		equ 44
p$zctc2		equ 48
p$zcio1		equ 78h		; Z8536 Counter/Timer & Parallel I/O	wbd
p$zscc1		equ 7Ch		; Z8530 Serial Communications Controller  wbd
p$sdvdb		equ 0		; SD VDB Board

	; diskette controller chip ports

p$fdcmnd	equ p$wd1797+0
p$fdstat	equ p$wd1797+0
p$fdtrack	equ p$wd1797+1
p$fdsector	equ p$wd1797+2
p$fddata	equ p$wd1797+3

	; parallel I/O 1

p$select	equ p$zpio1+0
p$fdint		equ p$zpio1+0
p$fdmisc	equ p$zpio1+1
p$zpio1a	equ p$zpio1+2
p$zpio1b	equ p$zpio1+3

	; counter timer chip 1

p$baudcon1	equ p$zctc1+0
p$baudlpt1	equ p$zctc1+2
p$index		equ p$zctc1+3


	; parallel I/O 2, Centronics printer interface

p$cent$stat	equ p$zpio2+0
p$cent$data	equ p$zpio2+1
p$zpio2a	equ p$zpio2+2
p$zpio2b	equ p$zpio2+3


	; dual asynch rcvr/xmtr, console and serial printer ports

p$crt$data	equ p$zdart+0
p$crt$stat	equ p$zdart+1
p$lpt$data	equ p$zdart+2
p$lpt$stat	equ p$zdart+3


	; Third Parallel I/O device

p$configuration	equ p$zpio3+0
p$bankselect	equ p$zpio3+1
p$zpio3a	equ p$zpio3+2
p$zpio3b	equ p$zpio3+3


	; Serial I/O device 1, printer 2 and console 4

p$lpt2data	equ p$zsio1+0
p$lpt2stat	equ p$zsio1+1
p$con4data	equ p$zsio1+2
p$con4stat	equ p$zsio1+3


	; Serial I/O device 2, console 2 an2 3

p$con2data	equ p$zsio2+0
p$con2stat	equ p$zsio2+1
p$con3data	equ p$zsio2+2
p$con3sta:	equ p$zsio2+3


	; second Counter Timer Circuit

p$baudcon2	equ p$zctc2+0
p$baudcon34	equ p$zctc2+1
p$baudlpt2	equ p$zctc2+2
p$rtc		equ p$zctc2+3


	; Z8536 Counter/Timer & Parallel I/O Chip

p$cioc		equ	p$zcio1+0
p$ciob		equ	p$zcio1+1
p$cioa		equ	p$zcio1+2
p$cioctl	equ	p$zcio1+3


	; Z8530 Serial Communication Controller Chip

p$sccb$stat	equ	p$zscc1+0
p$sccb$data	equ	p$zscc1+1
p$scca$stat	equ	p$zscc1+2
p$scca$data	equ	p$zscc1+3

p$scc$dcd	equ	8

p$sccb$rxmask	equ	1
p$sccb$txmask	equ	4 + p$scc$dcd
p$scca$rxmask	equ	1
p$scca$txmask	equ	4 + p$scc$dcd


	; SD VDB Board

p$vdb$data	equ	1
p$vdb$stat	equ	0

p$vdb$rxmask	equ	2
p$vdb$txmask	equ	4